64e54fda8d
fmcomms5: remove clock skew handling
...
Use SSI clock from master as SSI clock of slave.
2019-09-27 17:52:10 +03:00
95afc461a6
fmcomms5: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
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Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
48d2c9d36f
axi_ad9361: Define a MIMO enabled parameter
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Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
2019-06-10 15:16:47 +03:00
6e9bc398c3
fmcomms5: Connect overflow pin between adc_pack and adc_fifo
2019-02-14 14:36:45 +00:00
f79039b4d4
fmcomms5: Use new pack/unpack infrastructure
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Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
fa6f45a406
adrv936x, fmcomms2/5, usrpe31x: Fix warning on the dac path
...
Fix warnining regarding SYNC_TRANSFER_START parameter which doesn't
apply when the axi_dmac is configured for the tx path.
2018-08-20 14:29:57 +03:00
992011c3a3
fmcomms5: Connect the DAC data underflow
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Connect the DAC data underflow pin (fifo_rd_underflow) of the DMA
to the dunf pin of the device core. This way the software can detect
underflows in the DAC data path.
2018-04-13 18:46:29 +03:00
e4d71c99a6
fmcomms5- bd- data flow format
2017-08-07 11:25:55 -04:00
c9eaa43b1e
fmcomms5: Update UP instantiations
2017-04-21 15:10:44 +03:00
d46352928a
fmcomms5- fix ovf net connections
2017-02-02 14:24:06 -05:00
d2e7b6b635
fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-13 14:18:59 +02:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
35f6bd16e9
fmcomms5: Fixed reset connection for cpack core
2015-12-16 10:34:36 +02:00
6e549171f0
fmcomms5: Connected the clk input of the ad9361 to l_clk
2015-12-02 14:43:44 +02:00
c88cbf78af
fmcomms5: Added wfifo at the between AD9361 and cpack core
2015-11-13 15:50:32 +02:00
108ffebae4
fmcomms5: Updated project to 2015.2.1
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- added cpack / upack
2015-09-25 17:31:08 +03:00
39b032b868
fmcomms5: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:09 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
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The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
51b5e4ddc5
fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
2015-04-02 22:29:17 +03:00
92aa58826d
fmcomms5: Updated project to be compatible with both ZC702 and ZC706
2015-03-31 17:42:44 +03:00
1828a94446
fmcomms5: Updated common and ZC706 project to the latest framework
2015-03-25 17:42:11 +02:00
0ade2a5f67
fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints
2014-11-07 13:45:15 +02:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
bab90a19c2
fmcomms5/zc702: removed unused ila cores
2014-05-20 14:42:48 -04:00
9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00
Laszlo Nagy
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen
AndreiGrozav
Rejeesh Kutty