Commit Graph

5480 Commits (c5c772127dd791e07503ea53433b908ac81fb1c4)

Author SHA1 Message Date
Laszlo Nagy c5c772127d up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable
US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
2020-08-07 08:31:19 +03:00
Laszlo Nagy 37d378c753 common/ad_serdes_out.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
Laszlo Nagy 65d39b9164 common/ad_serdes_in.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
AndreiGrozav 4972e5c42d axi_dac_interpolate: oversampling optimization
Optimize the oversampling mechanism.
The behavior of the axi_dac_interpolate was changing if a debug module was
added to the core.
The current code has a better utilization and reliability.
2020-08-05 13:01:05 +03:00
AndreiGrozav d39ed3d4db axi_dac_interpolate: Fix oversampling by 2
When using an oversampling of 2 for axi_dac_interpolate the rate was
the same as with oversampling by 1(bypassing).

This commit removes the bypass for the ratio of 2.
2020-08-05 13:01:05 +03:00
AndreiGrozav a7a131cb36 ad_dds: Fix noise caused by dac_data_sync
For projects where the clock ratio between the sampling clock and core clock
is higher than 2, the ad_dds generates a number of samples equal with
the clock ratio. There is a phase offset between the samples, proportional
with the requested DDS frequency.
In scenarios where the DDS out frequency is closer to the upper
limit(Nyquist) and/or the clock ratio is also greater than 2 and the
dac_data_sync reminds low for an extended period of time, the DAC will
receive at each core clock period, a number of samples equal with the
clock ratio and with an amplitude influenced by the DDS out frequency.
In most cases similar with a sawtooth signal.

With this commit we ensures that samples received by the DAC are 0 for
the period where dac_data_sync signal is high. Only when the signal
transitions to low, the phase accumulator is initialized and the phase
information is passed to the phase to amplitude converter.

Another issue can appear when the sync signal is too short; less then
CLK_RATIO * clock cycles. Because the phase accumulator will not
synchronize at all stages, the final result will be a random combination of
sine-waves. Added a minimum sync pulse after the dac_data_sync is set
low.
2020-08-04 13:08:07 +03:00
Laszlo Nagy 6ca6257341 jesd204_rx: Increment version to 1.04.a
- support for frame alignment check
- support for interrupt on frame alignment error
- support for interrupt on unexpected lane status error
2020-07-31 11:43:41 +03:00
Laszlo Nagy 87b67ced17 jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
Laszlo Nagy 5e16eb85bb jesd204_rx: Generate interrupt on frame alignment error
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
2020-07-31 11:43:41 +03:00
Laszlo Nagy cf145ca961 axi_adxcvr: Reset status if PLL lock is lost
In case something happens with the reference clock of the CPLL or QPLL,
they might lose the locking. The status should reflect that.
2020-07-31 11:43:41 +03:00
Laszlo Nagy 15e14c76b9 jesd204_rx: Don't auto reset on frame alignment error by default
Let software handle the error case by default. Other steps might be
required to bring-up properly the link if one shot SYSREF is used.
2020-07-31 11:43:41 +03:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
AndreiGrozav ef5f29e66b m2k: Pattern Generator add instrument triggering
The Pattern generator is part of the axi_logic_analyzer core.
The trigger signal can be internal (Oscilloscope or Logic Analyzer) or
external(TI or TO pins).
2020-07-23 18:22:38 +03:00
AndreiGrozav ad4439433d axi_logic_analyzer: Add trigger disable condition
The trigger disable condition will be used as default
or last available option in the trigger out source selection.
2020-06-26 10:47:15 +03:00
AndreiGrozav 3e91078af0 axi_adc_trigger: Add trigger disable condition
Add trigger disable condition.
Set the trigger blocking/disable condition as the default condition in
the trigger selection multiplexer.
2020-06-26 10:47:15 +03:00
Laszlo Nagy 2e5a4eb684 jesd204: update README to reflect rev C 2020-06-23 13:52:35 +03:00
Istvan Csomortani 6c2b1b1634 fmcomms5/zc702: Fix the sys_dma_clk connections 2020-06-19 12:53:18 +03:00
Istvan Csomortani 51ebe6b35d spi_engine_execution: Latch sdx_enabled
The sdo_enabled and sdi_enabled control lines are generated from the
current state of the CMD bus.

In case of a delayed SDI latching the sdi_enabled can be deasserted at
the moment of the last valid bit, losing the generation of the sdi_data_valid
signal, which eventually cause a data loss, or even deadlock  on software driver.

To make the logic mode robust, latch the value of the CMD[9:8] at every
transfer command. Doing so the sdo_enabled and sdi_enabled control lines will
store the last active transfer command state and they will be
independent of the current state of the CMD bus. This way we can add
longer time delay to the SDI latching if it's necessary.
2020-06-18 15:46:06 +03:00
Istvan Csomortani e0d47645de spi_engine_execution: Optimize SDI latch delay logic 2020-06-18 15:46:06 +03:00
Istvan Csomortani 137c31db1d daq2/xilinx: Update project to use generic JESD204 TPL 2020-06-18 15:45:19 +03:00
Istvan Csomortani 299273f5a1 daq2/intel: Update project to use generic JESD204B TPL 2020-06-18 15:45:19 +03:00
Stanca Pop 847f0f22e6 cn0540: Fix typo 2020-06-04 18:38:14 +03:00
Stanca Pop 193fce338d cn0540: Initial commit 2020-05-28 18:49:35 +03:00
Stanca Pop 03ab28d7bf ad77681evb: Remove coraz7s project 2020-05-28 18:49:35 +03:00
Istvan Csomortani 71d500bdd4 adrv9009/intel: Use generic TPL cores 2020-05-26 16:22:30 +03:00
Laszlo Nagy 9c8190f709 adi_project_xilinx.tcl: discover all timing failures
Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
Istvan Csomortani 47a97aac7c adrv9371x/intel: Update project to use generic JESD204B TPL 2020-05-25 11:55:40 +03:00
Istvan Csomortani d4c393332a ad_ip_jesd204_tpl: TPL has and address space of 4KB 2020-05-25 11:55:40 +03:00
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy bff8a9fafb scripts/jesd204.tcl: rename tpl core instance
Having the same name for dac and adc TPLs creates conflict in the
address segment naming having random names associated to the segments.
This causes difficulties during scripting of the project in test bench
mode.
2020-05-20 19:08:25 +03:00
Laszlo Nagy db6af63583 scripts/adi_env.tcl: print in logs system variables are used 2020-05-20 19:07:23 +03:00
Istvan Csomortani e7600eb552 ad7616_sdz: Fix the project, after SDI ports were merged
Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
Istvan Csomortani 0402ce85e4 axi_spi_engine: Add pulse_width to the CNV configuration interface
The conversion start configuration interface can be used to configure
a PWM generator (util_pulse_gen) to generate CNV for a precission ADC.
2020-05-19 14:18:21 +03:00
Istvan Csomortani 2506239a8a spi_engine: Add an additional register for SDI data 2020-05-19 09:28:34 +03:00
Istvan Csomortani 88d97eb8a5 spi_engine: Add NUM_OF_SDI value into register map
The value of the HDL parameter NUM_OF_SDI can be read out from the
register at address 0x0C. The same register contains the value of the
DATA_WIDTH.
The register has the following bit layout:
  [15: 0]  DATA_WIDTH
  [23:16]  NUM_OF_SDI
  [31:24]  8'b0
2020-05-19 09:28:34 +03:00
Istvan Csomortani 4d54c7e2d6 spi_engine_execution: Merge the SDI lines into one vector
This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
Istvan Csomortani 7b3d52436a spi_engine: Forward the offload's sync_id to the register map
Forward the offload's sync_id to the register map, by defining an
additional AXI stream interface between the offload and axi_spi_engine.
The last sync_id of the offload module can read out from the
register 0x00C4. It also can generate and interrupt if the irq mask is
configured accordingly.
2020-05-19 09:27:28 +03:00
Istvan Csomortani 3a029fc1f0 spi_engine_execution: Define all wires before use 2020-05-19 09:27:28 +03:00
Istvan Csomortani 5493274fb7 spi_engine_offload: Define constraints for CDC 2020-05-19 09:27:28 +03:00
Istvan Csomortani ff4ce95110 axi_spi_engine: Improve constraints 2020-05-19 09:27:28 +03:00
Istvan Csomortani 3c193296dd spi_engine_offload: Increment sync_id per transfer
Increment the sync_id value at each transfer. Initial value of the
sync_id is the value of the last SYNC command loaded into the command
buffer.
2020-05-19 09:27:28 +03:00
AndreiGrozav e63478dbad library/scripts/adi_ip_xilinx: Fix critical warning 2020-05-18 14:22:59 +03:00
Arpadi 907d6fcbd9 sysid_intel: Fixed axi_sysid module name 2020-05-18 14:19:42 +03:00
Istvan Csomortani 6535e5b2ba scripts/xilinx: Version mismatch is upgraded to ERROR
There is a major compatibility issue between 2019.1 and 2019.2.

The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.

If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
Adrian Costina 10c9f7a70d ad_ip_jesd204_tpl_dac: Add option for an external synchronization pin
The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received

Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
2020-05-13 10:09:43 +03:00
Adrian Costina 5d4c6701d9 ad_ip_jesd204_tpl_adc: Add external synchronization
The external synchronization signal should be synchronous with the
adc clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received. While
the synchronization mechanism is armed, the adc_rst output signal is set

The current format should allow for the SYSREF signal to be used as
synchronous capture start, but will need to be disabled before the
synchronization mechanism is armed
2020-05-13 10:09:43 +03:00
sarpadi b92fb0a90d axi_fan_control: Fixed reset bug 2020-05-08 17:07:57 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Istvan Csomortani 8f2a223af9 spi_engine_execution: Fix the SDI latching
The commit 9ab88f1200 introduced a new
feature for the execution module, which provides the possibility to
delay the SDI line latch with one or more core clock cycle. Unfortunatly
the implementation was not correct and the SDI line was latched at the
wrong time.

This patch fix the aligment of the shift register and the SDI_DELAY parameter,
to latch the SDI line of the physical interface at the right time.

Improve the description of the feature.
2020-05-06 04:23:10 +01:00
Laszlo Nagy a32102b81c common/ad_iqcor: Fix for sample width smaller than 16
For converter resolution smaller than 16 when the core is disabled the
bypassed data was truncated. This patch should fix that.
2020-04-24 16:38:54 +03:00