zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,545 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

2 Commits (c46989e4e83bd11b725d87a6111c5fb628f0a603)

Author SHA1 Message Date
Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 2017-02-24 13:43:32 +02:00
Adrian Costina 9c975211da axi_dac_interpolate: Initial commit 2017-01-31 16:22:49 +02:00