pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	8ebc8fe4e2	updated makefiles	2016-12-09 23:06:41 +02:00
Adrian Costina	d60bce654c	Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools	2016-08-05 15:16:04 +03:00
Istvan Csomortani	64633e519c	Merge remote-tracking branch 'origin/dev_ad7616' into dev	2016-06-29 12:32:39 +03:00
Rejeesh Kutty	c293c04634	hdl make updates	2016-06-01 13:53:09 -04:00
Istvan Csomortani	4b962e8d72	spi_engine: The width of the counters depend on the current DATA_WIDTH	2016-01-20 15:44:06 +02:00
Istvan Csomortani	4e57170384	spi_engine: Update SPI Engine frame work + data width and number of SDI lines are configurable + axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)	2015-12-14 15:57:54 +02:00
Istvan Csomortani	a147acd791	spi_engine: Add support for multiple SDI lines. By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines. The supported number of SDI lines are: 1, 2, 3 and 4.	2015-11-02 18:42:55 +02:00
Istvan Csomortani	57cfb7cfb1	hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N	2015-08-19 14:11:47 +03:00
Lars-Peter Clausen	e6b58e8a20	Add SPI Engine framework SPI Engine is a highly flexible and powerful SPI controller framework. It consist out of multiple sub-modules which communicate over well defined interfaces. This allows a high degree of flexibility and re-usability while at the same time staying highly customizable and easily extensible. Currently included are four components: * SPI Engine execution module: The excution module is responsible for handling the low-level physical interface SPI logic. * SPI Engine AXI interface module: The AXI interface module allows memory mapped acccess to a SPI bus control stream and can be used to implement a software driver that controls the SPI bus. * SPI Engine offload module: The offload module allows to store a predefined SPI Engine command and data stream which will be send out when a external trigger signal is asserted. * SPI Engine interconnect module: The interconnect module allows to combine multiple control streams into a single stream giving multiple control modules access to a execution module. For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2015-05-21 17:21:35 +02:00

9 Commits (c39ed08edd16107b93e25443bbbc43bbea1c5895)