The axi_logic_analyzer does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.
Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.
This slightly reduces utilization by getting rid of some pipeline
registers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Adrian Costina