56a25afa68
common/vck190: Initial version
2021-10-05 14:09:51 +03:00
6a681b9e8d
common/vmk180_es1: Initial version
2021-10-05 14:09:51 +03:00
833e5f0aff
common/vmk180: Initial version
2021-10-05 14:09:51 +03:00
2fec1356d6
scripts/adi_project_xilinx.tcl: VCK190 support
2021-10-05 14:09:51 +03:00
222c5782b6
scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode
2021-10-05 14:09:51 +03:00
011c8c1f36
scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support
2021-10-05 14:09:51 +03:00
c22f622599
scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect
2021-10-05 14:09:51 +03:00
08c2ce75fe
scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect
2021-10-05 14:09:51 +03:00
aaaba50f83
scripts/project-xilinx.mk: Update target to xsa and cleanup list
2021-10-05 14:09:51 +03:00
0a986f76b8
scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl
2021-10-02 12:34:10 +03:00
0a3724e04c
s10soc: Update base desgin from ES to production, H-Tile version
2021-09-30 17:40:13 +03:00
5a3c3c878b
ad9213_dual_ebz: Initial commit
...
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout
avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
* sys_gpio_in 0x00000000
* sys_gpio_out 0x00000020
* sys_spi 0x00000040
* sys_gpio_bd 0x000000D0
* sys_id 0x000000E0
avl_mm_bridge_0 0x00040000 0x0007FFFF
* ad9213_rx_0.phy_reconfig_0 0x00000000
* ad9213_rx_0.phy_reconfig_1 0x00002000
* ad9213_rx_0.phy_reconfig_2 0x00004000
* ad9213_rx_0.phy_reconfig_3 0x00006000
* ad9213_rx_0.phy_reconfig_4 0x00008000
* ad9213_rx_0.phy_reconfig_5 0x0000A000
* ad9213_rx_0.phy_reconfig_6 0x0000C000
* ad9213_rx_0.phy_reconfig_7 0x0000E000
* ad9213_rx_0.phy_reconfig_8 0x00010000
* ad9213_rx_0.phy_reconfig_9 0x00012000
* ad9213_rx_0.phy_reconfig_10 0x00014000
* ad9213_rx_0.phy_reconfig_11 0x00016000
* ad9213_rx_0.phy_reconfig_12 0x00018000
* ad9213_rx_0.phy_reconfig_13 0x0001A000
* ad9213_rx_0.phy_reconfig_14 0x0001C000
* ad9213_rx_0.phy_reconfig_15 0x0001E000
* ad9213_rx_0.link_pll_reconfig 0x00020000
avl_mm_bridge_1 0x00080000 0x000BFFFF
* ad9213_rx_1.phy_reconfig_0 0x00000000
* ad9213_rx_1.phy_reconfig_1 0x00002000
* ad9213_rx_1.phy_reconfig_2 0x00004000
* ad9213_rx_1.phy_reconfig_3 0x00006000
* ad9213_rx_1.phy_reconfig_4 0x00008000
* ad9213_rx_1.phy_reconfig_5 0x0000A000
* ad9213_rx_1.phy_reconfig_6 0x0000C000
* ad9213_rx_1.phy_reconfig_7 0x0000E000
* ad9213_rx_1.phy_reconfig_8 0x00010000
* ad9213_rx_1.phy_reconfig_9 0x00012000
* ad9213_rx_1.phy_reconfig_10 0x00014000
* ad9213_rx_1.phy_reconfig_11 0x00016000
* ad9213_rx_1.phy_reconfig_12 0x00018000
* ad9213_rx_1.phy_reconfig_13 0x0001A000
* ad9213_rx_1.phy_reconfig_14 0x0001C000
* ad9213_rx_1.phy_reconfig_15 0x0001E000
* ad9213_rx_1.link_pll_reconfig 0x00020000
Connected directly to the h2s_lw_axi_master
* ad9213_rx_0.link_reconfig 0x000C0000
* ad9213_rx_0.link_management 0x000C4000
* ad9213_rx_1.link_reconfig 0x000C8000
* ad9213_rx_1.link_management 0x000CC000
* axi_ad9213_0.s_axi 0x000D0000
* axi_ad9213_1.s_axi 0x000D1000
* axi_ad9213_dma_0.s_axi 0x000D2000
* axi_ad9213_dma_1.s_axi 0x000D3800
2021-09-30 17:40:13 +03:00
8acf0296af
s10soc:ad_cpu_interconnect: Add an avl_address_width attribute
...
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.
The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
2021-09-30 17:40:13 +03:00
edd2956d58
data_offload: Fix util_[cu]pack offset to TDD syncs
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
b9554a9a5a
ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
58737e09ba
adi_project_intel.tcl: update quartus to 21.2
...
Update Quartus version to 21.2.0.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-09-30 09:53:53 +03:00
cfe0c0ced5
adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
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Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
b38747cefc
Make system: Be explicit in license that cover the make/build system
...
The build system is covered under a 1 Clause BSD license. Make sure
users are aware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:50:53 +03:00
1766b42a93
ad_mem_asym: Add option to control cascade layout
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
12b7fbb3a3
scripts: Add *.gen to clean list
2021-09-14 16:44:23 +03:00
cc68bd5198
fmcjesdadc1: Update block design ( #743 )
...
Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-09-08 17:19:57 +03:00
7423ecae14
data_offload: Improve external synchronization
...
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
16a93a804b
adrv9001[intel]: Add second pair of DMAs
...
fix observations for PR
2021-09-01 15:04:14 +03:00
fec4137046
ad400xx_fmc: Parametrize board select, sampling rate and adc resolution
...
fix comments
2021-09-01 15:03:10 +03:00
b7f34f7bd9
adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
...
The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.
This can be fixed/worked around with the proper reference clock
definition.
2021-08-20 10:46:09 +03:00
b354d517f5
daq2: Connected loose ad9144 dunf flag that fixes the critical warning
2021-08-20 10:38:52 +03:00
4cf53f373b
Revert "adrv9009zu11eg: Integrate data_offload"
...
This reverts commit 78999e154e
2021-08-19 21:43:09 +03:00
1f24344620
Update Quartus version to 20.4
...
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
b1d2a069e8
adi_make: Update bin build flow for 2020.1 tools
...
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
2021-08-10 17:44:30 +03:00
e9e278c898
ad9081_fmca_ebz: Remove bypass gpio
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2178191610
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
...
Memory requirements are the same as with the dacfifo (1 MiB).
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
564ef77588
data_offload: Calculate AXI_ADDRESS_LIMIT automatically
2021-08-06 11:55:24 +03:00
c82b0fb420
data_offload: Delete fifo_dst_rlast
2021-08-06 11:55:24 +03:00
4026f2d414
daq2/zc706: PL DDR size is 1GByte
2021-08-06 11:55:24 +03:00
703cc8a17e
data_offload_bd: Calculate the address limit from the address width
2021-08-06 11:55:24 +03:00
78999e154e
adrv9009zu11eg: Integrate data_offload
2021-08-06 11:55:24 +03:00
dc910420bd
daq2: Integrate data_offload
2021-08-06 11:55:24 +03:00
4c03580156
data_offload: Add integration process for Xilinx carriers
2021-08-06 11:55:24 +03:00
f2ca956d23
pluto: Fix dunf connection
2021-08-05 18:08:12 +03:00
bbb151f9f5
adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1
...
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
2021-07-29 14:06:42 +03:00
9d5de2fc21
Update Vivado version to 2020.2
...
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
2021-07-29 14:06:42 +03:00
907b750943
ad9083: Removed FIFO and increased DMAC transfer length
2021-07-28 12:45:20 +03:00
8343c03f5c
adrv9371x: remove IOB attribute from rx and rx_os
2021-07-26 12:42:21 +01:00
1158538753
adi_board: Fix ad_connect command tracing
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-07-22 15:02:36 +03:00
796af696da
ad_fmclidar1_ebz: Remove invalid ad_connect invocations
...
This commit removes two invalid ad_connect invocations, which weren't
caught in the original tests for commit cdda184007
2021-07-22 15:02:25 +03:00
a3e049ae03
scripts/adi_project_xilinx: Set number of parallel OOC jobs through environment variable
2021-07-13 10:09:08 +03:00
cdda184007
adi_board: Rewrite ad_connect to support all input permutations
...
The goal of this commit is to make sure there isn't any significance to
the order in which parameters of ad_connect are specified.
As an example, previously you could only `ad_connect target VCC`, while
`ad_connect VCC target` would fail.
Note: This code intentionally ignores bd_{,intf_}ports, because
these can all be treated as bd_pins.
Signed-off-by: David Winter <david.winter@analog.com>
2021-07-09 12:43:31 +03:00
63ac142874
adrv9001:a10soc:system_qsys.tcl: set clock polarity to 0
...
For fixing "Failed to reset the device and set SPI Config"
error, both clockPolarity and clockPhase should be disabled
or both enabled. By default both are unset.
Signed-off-by: Stefan Raus <stefan.raus@analog.com>
2021-06-16 11:42:50 +03:00
75b965e87f
ad9081_fmca_ebz/zcu102: Enable 204C modes
2021-06-10 09:53:43 +03:00
6637436c2e
scripts/adi_board.tcl: Use div2 out clock from xcvr in case of GTH and 204C
2021-06-10 09:53:43 +03:00
27465ce9c0
ad9081_fmca_ebz/zcu102: Fix spaces
2021-06-10 09:53:43 +03:00
7b7609d21a
ad469x: Clean system_project.tcl
2021-06-03 15:41:58 +03:00
d9bc014c98
adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode
2021-05-26 15:44:45 +03:00
568bef4a38
adrv9001/a10soc: Initial version
...
This project supports CMOS mode only.
2021-05-26 15:44:45 +03:00
5d008c3eca
Correct constraints file pin mapping
2021-05-25 16:27:58 +03:00
0ad691a603
ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate
2021-05-14 15:39:40 +03:00
8183599b51
ad9081_fmca_ebz/zcu102: Fix typo
2021-05-14 15:39:40 +03:00
cf7f45ffcc
ad9081_fmca_ebz: Fix for F=8
2021-05-14 15:39:40 +03:00
7b2ba41bdd
ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing
...
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
2021-05-14 15:39:40 +03:00
eba3409d78
ad9082_fmca_ebz: Use 9081 system_bd, updated comments
2021-05-14 15:39:40 +03:00
0d9e38bdbe
ad9081_fmca_ebz: Update path to common block design
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Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
2021-05-14 15:39:40 +03:00
680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
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The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
bd6ec360e2
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
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Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs
Organize XCVR params based on lane rate
2021-05-14 15:39:40 +03:00
693c002668
ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
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Remove Xilinx PHY and simplify project
2021-05-14 15:39:40 +03:00
d92f925b06
ad9081_fmca_ebz: Disable XBAR from DAC TPL
2021-05-14 15:39:40 +03:00
77a5edaa83
scripts/adi_board.tcl: In 204C do not connect SYNC
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Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
2021-05-14 15:39:40 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
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Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
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Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
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Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
...
The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
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Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
...
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
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Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
f73ed741c9
fmcadc5: Connect link clock to second JESD link layer
2021-02-05 15:24:15 +02:00
3f2f88ebbc
ad_fmclidar1_ebz: Set bits per sample towards the DMA interface
2021-02-05 15:24:15 +02:00
dafdd1c1e9
ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock
2021-02-05 15:24:15 +02:00
bb9eafceef
ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
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204B functional
204C functional
2021-02-05 15:24:15 +02:00
454b900f90
jesd204: Xilinx: NP=12 support
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To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
7be66b63c1
adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
2021-02-05 15:07:09 +02:00
6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
...
Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6e6c51dd27
common/a10soc: Bridge support
2021-02-05 10:24:59 +02:00
f0b753321a
common/intel: Add util_adcfifo integration script
2021-02-05 10:24:59 +02:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
Laszlo Nagy
LIacob106
Adrian Costina
Istvan Csomortani
David Winter
stefan.raus
Robin Getz
sergiu arpadi
hotoleanudan
Mihaita Nagy
AndreiGrozav
Owen McAree
vladimirnesterov