cc68bd5198
fmcjesdadc1: Update block design ( #743 )
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Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-09-08 17:19:57 +03:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
95249d2165
fmcjesdadc1: Update IP instantiations
2017-04-21 15:08:16 +03:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
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- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
hotoleanudan
sergiu arpadi
Istvan Csomortani
Adrian Costina