Adrian Costina
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021226bace
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util_var_fifo: Assign data_out and data_out_valid based on fifo_active
- fixed fifo_active assignments
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2017-04-18 12:17:40 +02:00 |
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Adrian Costina
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f761bf9bab
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util_var_fifo: Disable BRAMs if the depth of the FIFO is 0.
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2017-04-18 12:17:40 +02:00 |
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Adrian Costina
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20a223be99
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util_var_fifo: Move BRAM outside of the core so that it can be generated using Xilinx IP
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2017-04-18 12:17:40 +02:00 |
Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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Adrian Costina
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7387df9d13
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util_var_fifo: Initial commit
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2017-01-31 16:26:45 +02:00 |