c235e5e583
axi_pwm_gen: Initial commit
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axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-05-07 19:09:32 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
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Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
9413afa41c
jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
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get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
2021-03-22 10:55:00 +02:00
cdd6c92357
xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability
2021-03-22 10:17:10 +02:00
5f2681314f
xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit
2021-03-22 10:17:10 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
93044adddf
axi_spi_engine: almost full and almost empty is generated by the util_axis_fifo
2021-03-18 18:53:35 +02:00
d91b50071f
axi_spi_engine: Fix IRQ generation
2021-03-18 18:53:35 +02:00
22ce3ef9ce
axi_spi_engine: Fix level/room width for the CDC FIFOs
2021-03-18 18:53:35 +02:00
c718ba91f1
axi_adrv9001: Add status bit for Tx clocking
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If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.
This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
2021-03-17 16:34:12 +02:00
c9ca1ac00a
util_axis_fifo: Improve GUI layout in Vivado
2021-03-12 15:06:45 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
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Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
61c07ff9f1
util_axis_fifo: Add REMOVE_NULL_BEAT_EN feature
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If the REMOVE_NULL_BEAT_EN is set, in FIFO mode, all the beats with a
NULL TKEEP will be removed from the AXI stream.
This feature is used initially in data_offload, to create a continues and
cyclic TX data stream for DACs, when the IPs in the path have different data
widths.
2021-03-08 11:32:40 +02:00
9611be9ded
util_axis_fifo: Add TKEEP support
2021-03-08 11:32:40 +02:00
0d3d099beb
util_axis_fifo: Fix FIFO is full alignment
2021-03-08 11:32:40 +02:00
8ce1d6bf36
util_axis_fifo: Switch data and tlast order, improve maintainability
2021-03-08 11:32:40 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
e2a111d74b
jesd204/ad_ip_jesd204_tpl_dac: Drop LSBs from wider bus to be compatible with previous implementations
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Add selectable synthesis option for dropping LSBs or MSBs
2021-03-08 10:46:52 +02:00
69bb9df515
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-03-08 10:46:52 +02:00
8d388dd4f2
jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure
2021-03-08 10:46:52 +02:00
c2f703f56b
jesd204/jesd204_rx: Make output pipeline stages opt in feature
2021-03-08 10:46:52 +02:00
fd714c181a
jesd204/ad_ip_jesd204_tpl_adc: Make frame alignment opt-in feature
2021-03-08 10:46:52 +02:00
0db7519c18
jesd204_tx:64b: Remove reset
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Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
2545e53b0b
jesd204_rx:64b: Remove reset
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Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
7b4fa390db
ad_ip_jesd204_tpl_dac: fix capability reg
2021-03-08 10:46:52 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
85729def2a
axi_adrv9001: Double sync control lines between interface 1 and 2
2021-03-04 11:13:10 +02:00
c691b5b0af
axi_ad9361: Update constraints in case TDD is disabled
2021-03-04 11:13:10 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
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Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
50c4c3e815
axi_adrv9001: Fix channel 3 for Tx1 in DMA mode
2021-03-04 11:13:10 +02:00
3aa8a631d0
axi_adrv9001: Quartus 19.3 updates
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
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The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
4c0f9a65f1
axi_dmac: fix non-blocking assignment in combinatorial block
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Non-blocking assignments in combinatorial blocks can cause simulation problems. In this particular case iverilog coughed up a hairball.
2021-03-01 09:21:59 +02:00
bfd4c77284
jesd204/jesd204_tx: Expose character replacement capability
2021-02-26 14:41:49 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
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Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
77ef04201a
util_axis_fifo: Add almost empty and almost full support
2021-02-16 15:12:16 +02:00
6178b42ba2
library.mk: Update CLEAN_TARGET
2021-02-16 15:11:53 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
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This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
29d8c14e91
util_axis_fifo: Add TLAST to the streaming interfaces
2021-02-09 12:33:16 +02:00
b6fb5a9b5c
util_axis_fifo: Fix slave reset interface definition
2021-02-09 12:33:16 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
AndreiGrozav
Laszlo Nagy
vladimirnesterov
Sergiu Arpadi
stefan.raus
Istvan Csomortani
Aaron Holtzman