8879218502
a5gte: Fixed timing violations
2016-12-16 15:37:51 +02:00
596d0fa3fb
axi_ad9122: Add a constraint for a false path
2016-12-16 12:07:40 +00:00
a00d9870be
axi_ip_constr: Fix constraints
...
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
c0b0f9b7e9
ad6676evb: Connect SYS_REF to GPIO
2016-12-14 17:55:50 +02:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
3a2c889115
ad6676evb: Update GT configuration
2016-12-14 17:55:49 +02:00
905c7ccf99
Merge branch 'hdl_2016_r2' into dev
...
Merging commmits : c455d2d88461411515b6fd5165cad962614
2016-12-13 19:48:47 +02:00
d962614000
usdrx1/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
1515b6f1af
fmcomms7/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:18:18 +02:00
8846141467
fmcomms1/kc705: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:16:31 +02:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
9fb7db97da
a5gte: Fixed timing violations
2016-12-13 10:30:24 +02:00
99f72a9b3b
util_gtlb: this core is obsoleted
...
The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
2016-12-12 14:23:47 +02:00
5c8dde8483
util_jesd_gt: this core is obsoleted
...
The util_jesd_gt core is obsoleted by xilinx/util_adxcvr and altera/avl_adxcvr
2016-12-12 14:15:38 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
06aab8ebbd
pzsdr1: Set the device core to 1R1T mode
2016-12-09 16:35:46 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
23c91ca48a
pzsdr1/lvds: The interface runs at max 122.88 MHz
2016-12-09 11:45:11 +02:00
f799c40cf0
usdrx1/a5gt- xcvr interface changes
2016-12-08 16:05:23 -05:00
854cd44026
ad9671- xcvr interface changes
2016-12-08 16:05:23 -05:00
c114888956
usdrx1- updates
2016-12-08 16:05:23 -05:00
b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
252c67ceff
fmcomms6: Delete project
...
This project will not be supported in further releases.
2016-12-08 17:22:41 +02:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
801da3cb25
daq3/kcu105- fix timing violations
2016-12-06 12:31:40 -05:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
8f94103f8b
daq1/a10gx: Makefile fix
2016-12-06 15:24:23 +02:00
95ee7c093c
daq1/a10gx: Update system_bd port names
2016-12-06 15:24:23 +02:00
b7143a7a3b
daq1/a10gx: Update IO pin assignments
2016-12-06 15:24:22 +02:00
a415625069
daq1/a10gx: Add spi wrapper file to the project
2016-12-06 15:24:22 +02:00
e30a80fda0
daq1_spi: Delete device specific macro instantiation
2016-12-06 15:24:21 +02:00
977e6d9189
adi_ip_alt: Fix some typo
2016-12-06 15:24:21 +02:00
7876c8ffa4
axi_ad9684: Add loaden and phase ports for altera support
2016-12-06 15:24:20 +02:00
a7d3df8757
axi_ad9684: Update hw tcl script for altera
2016-12-06 15:24:20 +02:00
b0a5be8565
axi_ad9122: Add loaden port for altera support
2016-12-06 15:24:20 +02:00
cedca30cd6
axi_ad9122: Update hw tcl script for altera
2016-12-06 15:24:19 +02:00
0715c962f1
altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in
2016-12-06 15:24:19 +02:00
6cf9df50e3
altera/ad_serdes: Define DEVICE_FAMILY in hw script
2016-12-06 15:24:18 +02:00
7a8dc92b84
usb_fx3: Add interrupt monitor and increase ILA data depth
2016-12-06 11:55:28 +02:00
1e4bdea80c
usrpe31x: Fix Makefile
2016-12-06 11:07:42 +02:00
4b7bf422ee
pzsdr2/ccbox- remove imu intr on pl
2016-12-05 10:21:42 -05:00
351811e13f
pzsdrx/ccbox- imu intr on gpio
2016-12-05 10:18:40 -05:00
8b8c37e2e2
scripts/adi_ip: Remove AXIMM inference from adi_ip_infer_interfaces
...
The AXI Memory Map interface is infered in the adi_ip_properties process.
Infer it again in the adi_ip_infer_interfaces brakes the flow,
the tool will not find the cell's address segment, so there will not be
any address space assigned to the AXI interface.
Affected cores were axi_i2s_adi and axi_spdif_tx.
2016-12-05 14:33:39 +02:00
753f4bd06e
axi_intr_monitor: Slightly modify counter start points
...
Start the counter_to_interrupt_cnt counter when the counter_to_interrupt
value is written to the register map. This gives applications better
control over when the counter starts counting.
Also start the counter_from_interrupt on the rising edge of the interrupt
signal to avoid bogus values.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 20:09:29 +01:00
334ce5ddc0
axi_intr_monitor: Fully register IRQ output signal
...
The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.
This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 19:28:13 +01:00
Adrian Costina
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Lars-Peter Clausen