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12 Commits (c0184bce591dbda739aab28a7afad20cc3c61f20)

Author SHA1 Message Date
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions 
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
 2018-04-11 15:09:54 +03:00
AndreiGrozav dd8d6f90ee zcu102:all_projects: Delete required version tcl variable 
All the ZCU102 projects will use the default tool version.
This setup was a temporary exception for hdl_2017_r1 release.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands 
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
 2018-03-07 07:40:19 +00:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2018-01-09 15:20:06 +01:00
AndreiGrozav a23c640180 Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
AndreiGrozav f1e51a8b89 adrv9371x_zcu102: Fix rx_div_clk constraint placement 2017-11-20 15:36:51 +00:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects 
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen caac2ce588 adrv9371x: zcu102: Fix lane mapping 
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.

Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider 
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
AndreiGrozav 22808fa03c zcu102: Update to rev 1.0 2017-11-08 10:33:12 +02:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00