Commit Graph

33 Commits (bfcc3696e48c2788db25743f4b1a825866306dd2)

Author SHA1 Message Date
Rejeesh Kutty 1d9a8a24dc adi_board- create_bd_cell replacement 2017-04-11 14:26:02 -04:00
Rejeesh Kutty 820874ef93 adi_board- add auto ip version handling 2017-04-06 13:02:17 -04:00
Rejeesh Kutty 3e57ff1fc5 z-mpsoc- map 0x4-0x8,0x7-0x9 2016-12-20 16:14:38 -05:00
Rejeesh Kutty 22e230618c scripts/adi_board.tcl- support multiple xcvrs 2016-11-23 16:22:05 -05:00
Rejeesh Kutty 8f562fd069 xcvr updates- board procedure 2016-11-22 14:43:36 -05:00
Rejeesh Kutty 750b23621b board-tcl: xcvr qpll/cpll changes 2016-11-22 12:53:02 -05:00
Rejeesh Kutty 4a5b7fc723 scripts- reconnect added 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 79b9e21be8 board- xcvr procedure 2016-09-26 15:20:18 -04:00
Istvan Csomortani cd0c981b50 projects/scripts: Fix to prevent a warning
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
Istvan Csomortani 6ab137a0e9 projects/scripts: Cosmetics 2016-08-26 10:07:08 +03:00
Adrian Costina f1b834ab25 scripts: Update script so that all interconnects are optimized for performance 2016-08-22 16:56:02 +03:00
Shrutika Redkar 3b2bde2fa1 hdl-vivado-2016.2- min. addr-space requirement 2016-07-28 13:44:57 -04:00
Rejeesh Kutty 16e3a0e569 zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty bf6ef4e5f3 board- add disconnect 2016-04-11 15:33:00 -04:00
Lars-Peter Clausen c53f8c15ee Add CN0363 project
Add support for the CN0363 (colorimeter) board connected to the ZED board.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Rejeesh Kutty ee2cd034bc scripts: add gnd/vcc connections 2015-03-26 10:08:01 -04:00
Istvan Csomortani f7dd466469 adi_board.tcl : Fix some issue with the ad_mem_hpx_interconnect
Sometimes the find_bd_objs does not do its job, so need to double check that the interface clock is already connected to the p_clock or not.
Not sure about the cause of this behavior, need more investigation. Issue was found first at KC705 base design.
2015-03-13 18:51:21 +02:00
Rejeesh Kutty 17d8c1b72b daq2: move intrs into ipi 2015-03-12 16:17:17 -04:00
Rejeesh Kutty c0eef42647 adi_board: enable ps7 hp if needed 2015-03-09 16:12:23 -04:00
Rejeesh Kutty ed28b47203 board: optimize interconnect for performance 2015-03-06 12:38:52 -05:00
Rejeesh Kutty 0ac1676318 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 0258afbadc board: add ddr seg variable 2015-01-09 14:12:50 -05:00
Rejeesh Kutty c1268f089d scripts: hp/mem updates 2014-11-10 15:06:20 -05:00
Rejeesh Kutty fd66affa42 scripts: add default memory interconnect 2014-10-27 15:53:20 -04:00
Rejeesh Kutty fc4e002150 scripts: add mb cpu side 2014-10-27 15:53:19 -04:00
Rejeesh Kutty 210da4116f scripts: initial commit 2014-10-03 16:13:34 -04:00
Istvan Csomortani 179d6d601c adi_board.tcl : Use 'global' instead of '$::' 2014-04-14 11:45:35 +03:00
Istvan Csomortani c718169f27 adi_board.tcl : Fix the address assignment command
A lot of cores have more than one address segments, therefor need
	to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
Istvan Csomortani cf5b9b51fd adi_board.tcl : Fix spi ports and hp clocks 2014-04-11 15:31:12 +03:00
Istvan Csomortani 37e2059fd0 adi_board.tcl : General update
- Split the adi_dma_interconnect to two procedure:
	  adi_dma_interconnect and adi_hp_assign
	- Fix the adi_spi_core
	- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
Istvan Csomortani 8deb36ce08 adi_board.tcl: All procedures works on Zynq/Microblaze
General patch for the integration procedures. Tested on kc705 and
	zed.
2014-04-01 16:19:24 +03:00
Istvan Csomortani 4ef88a3bed adi_board.tcl : Patch for adi_spi_core process
- Fix indentation
	- Pacth for adi_spi_core process
2014-03-31 16:41:07 +03:00
Istvan Csomortani 7f4f200fce Project scripts: Initial check in of adi_board.tcl
The script contains integration tcl processes.
2014-03-26 19:08:56 +02:00