Commit Graph

37 Commits (bad1d0367891999b376782f89f5609fd543c0408)

Author SHA1 Message Date
kylex 365933542d
scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.

Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-10-30 09:48:32 -03:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Alin-Tudor Sferle a031cba1d5 project_xilinx.tcl: Fix the regex expression for Kria KV260 evaluation board 2023-07-19 11:32:10 +03:00
alin724 0f3462c83b template_kv260: Add template design for kv260 evaluation board 2023-05-12 16:06:19 +03:00
Stanca Pop 1c8f210baf adi_project_xilinx.tcl: Add matlab env variables
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.

The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.

The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
2023-04-21 15:41:42 +03:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
alin724 6aa899f161 scripts/adi_project_xilinx.tcl: Add new constraints file support 2022-07-20 14:36:04 +03:00
Laszlo Nagy 88b5c2d6db projects/common/vcu128: Initial VCU128 support 2021-11-19 18:08:16 +02:00
hotoleanudan 1bc8a41aea
vc709_carrier: Add vc709 carrier (#788)
Added vc709 carrier to the projects/common folder location.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-02 12:05:42 +02:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 2fec1356d6 scripts/adi_project_xilinx.tcl: VCK190 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 222c5782b6 scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode 2021-10-05 14:09:51 +03:00
Laszlo Nagy 011c8c1f36 scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support 2021-10-05 14:09:51 +03:00
stefan.raus cfe0c0ced5 adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
stefan.raus bbb151f9f5 adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
2021-07-29 14:06:42 +03:00
stefan.raus 9d5de2fc21 Update Vivado version to 2020.2
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
2021-07-29 14:06:42 +03:00
Laszlo Nagy a3e049ae03 scripts/adi_project_xilinx: Set number of parallel OOC jobs through environment variable 2021-07-13 10:09:08 +03:00
Istvan Csomortani 9ec3408c79 adi_project_xilinx: Fix the adi_project process
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.

NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
Sergiu Arpadi c54552d823 adi_project_xilinx: Add env var
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl

projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
Arpadi 51b5e4f58b tcl: Change Vivado version to 2020.1
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
aholtzma bab3426f91 scripts: allow directly specifying a device when creating a project
Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
Laszlo Nagy 9c8190f709 adi_project_xilinx.tcl: discover all timing failures
Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
Istvan Csomortani 6535e5b2ba scripts/xilinx: Version mismatch is upgraded to ERROR
There is a major compatibility issue between 2019.1 and 2019.2.

The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.

If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
Sergiu Arpadi 3192807f22 adi_project_xilinx: Fixed variable name 2020-02-14 11:22:46 +02:00
Sergiu Arpadi c5e03eb196 adi_project_xilinx: Added power analysis procedure 2020-02-14 11:22:46 +02:00
sraus 78a1e54a33 adi_project_xilinx.tcl: Generate resource utilization for IPs 2020-02-13 11:33:02 +02:00
Sergiu Arpadi 135538b521 adi_project: Fixed kcu105 board file selection 2020-01-16 17:16:58 +02:00
Sergiu Arpadi e773b22087 adi_project: Updated board files version selection
vivado will automatically select the latest version for a given board
2020-01-14 17:16:01 +02:00
Istvan Csomortani 34ea5efdff adi_project_xilinx: Use the latest board files 2020-01-13 12:25:23 +02:00
Istvan Csomortani adfeb435a4 scripts: Update Vivado version to 2019.1 2020-01-13 12:25:23 +02:00
Stanca Pop 40d839df5f coraz7s: Initial commit 2019-11-15 14:35:00 +02:00
Stefan Raus fd4d32c408 projects/scripts/*xilinx*: Generate report utilization extra files
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
Istvan Csomortani 75d263afc5 adi_project_xilinx: Add constraint files to constr_1 file set 2019-09-27 18:21:25 +03:00
Istvan Csomortani fa610d36c6 ad_ghdl_dir: Fix global variable name
In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00