39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
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Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
10c21a343a
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
2014-07-08 10:07:31 +03:00
c53b257ab1
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
2014-07-07 22:28:25 +03:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
9a08189b93
c5soc: initial a5soc copy
2014-07-01 13:09:38 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
2837d788a6
mitx045: Added I2S core to the base design
2014-06-06 17:53:47 +03:00
f217139770
fmcomms2: added project for mini_itx, xc7z045 version
2014-06-02 14:06:10 +03:00
1d53d79e25
fmcomms2/common: Fix ad9361's interface
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Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
synchronize the cores in case of a multiple device configuration.
2014-05-21 10:09:54 +03:00
25e4520726
fmcomms2/common: Delet trailing white spaces
2014-05-21 09:47:37 +03:00
51c0ee1e20
ml605: tcl updates
2014-05-06 09:29:21 -04:00
e7cbaca216
ml605: initial checkin
2014-05-05 11:24:12 -04:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
9676146725
FMCOMMS2 AC701 Project
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Not tested - must program Vadj on board
2014-04-01 15:35:44 +03:00
e597467447
FMCOMMS2 VC707 Project
2014-04-01 15:34:29 +03:00
814b0d72d6
Modified Reset signals for FMCOMMS2 base design
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Made all resets the same (sys_100m_resetn)
2014-04-01 15:32:48 +03:00
f8c1179bc1
FMCOMMS2 KC705 Project.
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Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
2014-03-24 11:48:52 +02:00
31a1ff384d
FMCOMMS2 Base Design tcl modified
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Added support for both Zynq and MicroBlaze projects
2014-03-21 09:57:52 +02:00
2c898bf3a2
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
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ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00
ee56db8d50
FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
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tcl: FCLK2 was modified from 100 MHz to 125 MHz.
xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
a6c3cb29c6
Modified SPI and ILA in fmcomms2_bd.tcl
2014-03-12 16:52:22 +02:00
66c6b2b182
fmcomms2: added
2014-03-11 20:04:26 -04:00
Adrian Costina
dbogdan
Rejeesh Kutty
Istvan Csomortani
ATofan