Commit Graph

84 Commits (bad1d0367891999b376782f89f5609fd543c0408)

Author SHA1 Message Date
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Istvan Csomortani 391ac468a7 adrv9009/common: Fix ad_xcvrcon proc call
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
Laszlo Nagy c930395773 adrv9009:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 0b66b39352 adrv9009/zc706: make SPI selection consistent 2018-12-21 17:32:48 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL
Make the block design parametrizable.
Limitations:
  F = 1,2,4
2018-12-21 17:32:48 +02:00
Laszlo Nagy 47093775ae adrv9009/zc706: top level cleanup 2018-12-21 17:32:48 +02:00
Laszlo Nagy 8adc285eab adrv9009/zc706: fix location constraints 2018-12-21 17:32:48 +02:00
Laszlo Nagy 7a5a8c5340 Revert "adrv9009: Removed ZC706 based project"
This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
2018-12-21 17:32:48 +02:00
Adrian Costina e09f3290ff adrv9009: Move intel project to upack2/cpack2 2018-12-03 12:23:24 +00:00
Lars-Peter Clausen 2462f8e50f adrv9009: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Adrian Costina 401395cdd1 adrv9009: A10GX: Initial commit 2018-11-27 15:31:21 +02:00
Adrian Costina e4048c7b04 adrv9009: A10SOC: Add second observation channel 2018-11-27 15:31:21 +02:00
Adrian Costina f12bd3d246 adrv9009: A10SOC: Initial commit 2018-11-27 15:31:21 +02:00
Istvan Csomortani 559e00fd75 adrv9009/zcu102: Increase DAC buffer depth to 18Mb 2018-10-11 16:57:30 +03:00
Istvan Csomortani 1931d65b7a adrv9009/zcu102: Update initial configuration for GT clock output control 2018-10-04 14:37:02 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy 05789e8978 adrv9009/adrv9371x/fmcomms2:Drop usage of ad_iobuf on non-bidirectional IOs
Some projects use the ad_iobuf on IOs that are not bidirectional
producing synthesis warnings.

The change fixes warnings like:
[Synth 8-6104] Input port 'gpio_bd_i' has an internal driver
[Synth 8-6104] Input port 'gpio_status' has an internal driver
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Adrian Costina 41e717ec2c adrv9009: Added option for enabling the second observation channel 2018-06-29 11:10:39 +03:00
Adrian Costina e982232d75 adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs 2018-06-12 23:53:56 +03:00
Adrian Costina f3ac5d3ad3 adrv9009: Increase all DMAs MAX_BYTES_PER_BURST to 256 2018-06-12 23:53:56 +03:00
Adrian Costina 801351d93c adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations 2018-06-12 23:53:56 +03:00
Adrian Costina cc18f76e3b adrv9009: Reduced DAC FIFO size, as it's not useful for real applications and the memory can be used in other parts of the design 2018-06-12 23:53:56 +03:00
Adrian Costina 65c765eb33 adrv9009: Increase DMA FIFO sizes 2018-06-12 23:53:56 +03:00
Adrian Costina 4999a52f87 adrv9009: Removed ZC706 based project 2018-05-14 11:36:31 +03:00
Adrian Costina e445fbe04f adrv9009: Improved data throughput and DAC FIFO size
Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA
HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time.
HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller
All HPx and DMA buswidths have been increased to 128 bits
The HPx-DMA clock has been increased to 300 MHz
DAC FIFO address size has been increased to 17
2018-05-14 11:33:04 +03:00
Adrian Costina e4d579726d Renamed ad9379 to adrv9009 2018-04-26 18:19:11 +03:00