Commit Graph

23 Commits (bad1d0367891999b376782f89f5609fd543c0408)

Author SHA1 Message Date
Iulia Moldovan 0590a4046c Add copyright & license for all files needing ADI JESD specific license
* Added every year when the file was edited, with comma
 * Range if it's consecutive years

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-09-07 10:45:49 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy c39b6b2ac8 jesd20r_rx/jesd204_tx: Support for F=64 2021-07-27 11:31:19 +03:00
Laszlo Nagy c2f703f56b jesd204/jesd204_rx: Make output pipeline stages opt in feature 2021-03-08 10:46:52 +02:00
Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers
Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 454b900f90 jesd204: Xilinx: NP=12 support
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.

e.g  Input datapath width = 4; Output datpath width = 6;
  for F=3 one beat contains 2 frames
  for F=6 one beat contains 1 frame

The width change is realized with a gearbox.

Due the interface width change the single clock domain core is split
in two clock domains.
  - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
  -              lane rate / 20 for input datapath width of 8 octets 8b10b
  -              lane rate / 66 for input datapath width of 8 octets 64b66b

  - Device clock : Link clock * input data path width / output datapath width

Interface to transport layer and SYSREF handling is moved to device clock domain.

The configuration interface reflects the dual clock domain.

If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 6ef803e7ab jesd204: Make character replacement opt in feature
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.

If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
2021-02-05 15:24:15 +02:00
Matt Blanton 7093e10ebf jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports 2021-02-05 15:24:15 +02:00
Matt Blanton 400c3927f7 jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
2021-02-05 15:24:15 +02:00
Laszlo Nagy e759c1855b jesd204: Clean-up combinatorial logic
To correctly model combinatorial logic in always blocks
blocking assignments must be used.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 7c523fbf02 jesd204_rx: Reset frame alignment monitor event generator
If the link is not enabled no event should be generated.
2020-09-29 17:27:42 +03:00
Laszlo Nagy aa4de79045 jesd204/jesd204_rx: Ignore frame alignment errors if lane is not in DATA phase
If the lane looses synchronization due invalid characters or disparity
error the lane alignment monitor checks random input which results in
irrelevant reporting of frame alignment error.
2020-09-29 17:27:42 +03:00
Laszlo Nagy d825fffd62 jesd204/jesd204_rx: Reset error counter once all lanes synced
If all lanes are synchronized (CGS state machine is in DATA phase) for long
enough therefore the link is also synchronized/DATA phase reset the error
counter since the accumulated values during INIT/CHECK are irrelevant.
These errors are handled by the per-lane CGS state machine.

All errors accumulated during INIT/CHECK phase of CGS are relevant only
if the link is unable to reach the DATA phase.
The link stays in DATA phase unless software resets it,
so all errors accumulated during the DATA phase are relevant.
2020-09-29 17:27:42 +03:00
Laszlo Nagy 87b67ced17 jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
Laszlo Nagy 5e16eb85bb jesd204_rx: Generate interrupt on frame alignment error
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
2020-07-31 11:43:41 +03:00
Laszlo Nagy 15e14c76b9 jesd204_rx: Don't auto reset on frame alignment error by default
Let software handle the error case by default. Other steps might be
required to bring-up properly the link if one shot SYSREF is used.
2020-07-31 11:43:41 +03:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Laszlo Nagy d1072847df jesd204_rx: 64b mode support for receive peripheral
Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
Laszlo Nagy b90c2e79dc jesd204_rx: add parameter for input pipeline stages
Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Adrian Costina 3b9f733408
jesd204: Add RX error statistics (#98)
* jesd204: Add RX error statistics

Added 32 bit error counter per lane, register 0x308 + lane*0x20

On the control part added register 0x244 for performing counter reset and counter mask
Bit 0 resets the counter when set to 1
Bit 8 masks the disparity errors, when set to 1
Bit 9 masks the not in table errors when set to 1
Bit 10 masks the unexpected k errors, when set to 1

Unexpected K errors are counted when a character other than k28 is detected. The counter doesn't add errors when in CGS phase

Incremented version number
2018-05-07 15:33:00 +03:00
Istvan Csomortani 0e099b6f08 jesd204_rx: Add dynamic multi-link support
A multi-link is a link where multiple converter devices are connected to a
single logic device (FPGA). All links involved in a multi-link are synchronous
and established at the same time. For a RX link this means that the SYNC signal
needs to be propagated from the FPGA to each converter.

Dynamic multi-link support must allow to select to which converter devices on
the multi-link the SYNC signal is propagated too. This is useful when depending
on the usecase profile some converter devices are supposed to be disabled.

Add the cfg_links_disable[0x081] register for multi-link control and
propagate its value to the RX FSM.
2018-05-03 18:48:54 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00