Alin-Tudor Sferle
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119d4e43a3
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axi_pwm_gen: Add support for 16 channels
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
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2023-12-15 15:03:07 +02:00 |
Sergiu Arpadi
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369e34425f
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axi_pwm_gen: Update timing constraints, hw.tcl and sdc files.
Not using util_cdc_constr.tcl
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2023-03-30 14:55:59 +03:00 |
Jem Geronimo
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2db944396f
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axi_pwm_gen: add: intel support (#1080)
Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
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2023-02-07 18:27:04 +08:00 |
Iulia Moldovan
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db94628cc6
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library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-01-27 11:54:05 +02:00 |
Adrian Costina
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591a23156b
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Makefiles: Update header with the appropriate license
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2021-09-16 16:50:53 +03:00 |
AndreiGrozav
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c235e5e583
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axi_pwm_gen: Initial commit
axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
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2021-05-07 19:09:32 +03:00 |