Commit Graph

1228 Commits (bab9b2df0b476886644a64681afec2a97470451c)

Author SHA1 Message Date
Istvan Csomortani 1b9d2d434c axi_ad9361_tdd: Delete unused register 2016-10-05 17:41:08 +03:00
Adrian Costina ddceff2b5c axi_usb_fx3: Updated header/footer signature 2016-10-04 16:11:24 +03:00
Rejeesh Kutty 48dd4880a3 util_adxcvr- ultrascale+ initial commit 2016-10-03 16:11:45 -04:00
Rejeesh Kutty 0e8551545c util_adxcvr- ultrascale+ initial commit 2016-10-03 16:11:45 -04:00
Rejeesh Kutty b4652650e4 util_adxcvr- xcvr_type parameter 2016-10-03 16:11:45 -04:00
Rejeesh Kutty 63ddcf1e26 util_adxcvr- synthesis warnings fix 2016-10-03 16:11:45 -04:00
Adrian Costina 8e0dc859af axi_usb_fx3: Update
- added 1 clock delay for slrd_n signal
- rearrange databytes
2016-10-03 15:17:01 +03:00
Istvan Csomortani 43b3761b80 axi_ad9361: Flop the tx and rx valid 2016-10-03 12:24:04 +03:00
Istvan Csomortani 8e25bc01b3 all: Change tab to double space
Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
2016-10-01 18:13:42 +03:00
Rejeesh Kutty 6b956066ef xilinx/ad_lvds*- ultrascale+ 2016-09-30 11:55:10 -04:00
Rejeesh Kutty e9105faae1 library/scripts- add beta devices 2016-09-30 11:55:10 -04:00
Costina c072c2f89a util_clkdiv: Add IP 2016-09-30 17:13:51 +03:00
Rejeesh Kutty 7290bcc81a hdlmake- updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty ffec95f220 ad9371- xcvr updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty b4fac96aad axi_ad9361- independent disables 2016-09-28 15:45:27 -04:00
Istvan Csomortani f7fb3ccaca axi_ad9361: Change the data path gating
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
Istvan Csomortani df485d7878 axi_ad9684: Fix the PN9 PRBS sequence monitor 2016-09-28 10:47:16 +03:00
Rejeesh Kutty 9defccef70 dacfifo- axi address map fixes 2016-09-27 14:48:23 -04:00
Rejeesh Kutty c98e2e95dd ad9162- xcvr updates 2016-09-26 15:21:45 -04:00
Rejeesh Kutty 692cb10fb2 ad9625- xcvr updates 2016-09-26 15:21:11 -04:00
Istvan Csomortani ad16aec101 axi_ad9684: Fix SERDES modules 2016-09-26 11:14:35 +03:00
Rejeesh Kutty f6c7aa9005 library- dac parameter changes 2016-09-23 16:15:59 -04:00
Rejeesh Kutty 1a11e28821 ad9361- dac data path split 2016-09-23 16:13:46 -04:00
Rejeesh Kutty 6735333aea common- dac data path split 2016-09-23 16:13:24 -04:00
Rejeesh Kutty 6837143110 library/ adc parameter changes 2016-09-23 13:44:47 -04:00
Rejeesh Kutty 7be6168b2e ad9361- adc data path split 2016-09-23 13:42:14 -04:00
Rejeesh Kutty 8729af1b91 common- adc- data path disable split 2016-09-23 13:40:35 -04:00
Rejeesh Kutty 78f7384150 ad9361- vivado synthesis warnings fix 2016-09-22 13:41:18 -04:00
Istvan Csomortani 2b6eb1d65e up_drp: Revert some bit locations
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
Rejeesh Kutty 21b5e9c634 hdlmake- updates 2016-09-21 11:56:03 -04:00
Rejeesh Kutty 0def596b43 axi_xcvrlb- updates 2016-09-21 11:04:22 -04:00
Rejeesh Kutty d497a7b0ae axi_xcvrlb- constraints 2016-09-21 11:04:22 -04:00
Istvan Csomortani a21b9fe8ff up_drp: Fix up_drp_wr 2016-09-21 17:55:58 +03:00
Istvan Csomortani 64cd7dc002 axi_ad9122: Update core to the new DRP interface 2016-09-21 16:09:55 +03:00
Istvan Csomortani bae839acd4 axi_ad9739a: Update core to the new DRP interface 2016-09-21 15:23:08 +03:00
Istvan Csomortani 781702c1b9 axi_ad9434: Update the core to the new DRP interface 2016-09-21 15:12:59 +03:00
Istvan Csomortani 913eafed48 up_drp : Update the DRP interface to support Altera platforms 2016-09-21 15:00:45 +03:00
Dragos Bogdan 10408b8c88 up_tdd_cntrl: Set PCORE version to 1.00.a 2016-09-21 10:27:28 +03:00
Rejeesh Kutty 1860d72df6 axi_xcvrlb- updates 2016-09-19 12:39:59 -04:00
Rejeesh Kutty 5592c2780e axi_xcvrlb- loopback version 2016-09-19 12:39:59 -04:00
Istvan Csomortani 38f1521861 xilinx/ad_serdes_in : Fix some typos 2016-09-19 16:02:52 +03:00
Istvan Csomortani ff0f659a33 xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE 2016-09-19 16:02:06 +03:00
Istvan Csomortani 2159f78c80 axi_ad9361: Delete invalid assignment of a generated wire 2016-09-16 17:38:08 +03:00
Istvan Csomortani 6510f92c12 ad_serdes : Cosmetic changes 2016-09-16 14:45:39 +03:00
AndreiGrozav 13a35f7a2a altera/ad_serdes_clk: The IO_PLL reset is active heigh 2016-09-16 14:20:39 +03:00
Istvan Csomortani 858ea09048 altera/ad_serdes_in: Fix some typos 2016-09-16 10:56:16 +03:00
Rejeesh Kutty a2d15acb89 ad_serdes- altera/xilinx sync 2016-09-15 13:33:55 -04:00
Rejeesh Kutty 63696c1a28 alt_serdes- data-width parameter 2016-09-15 11:12:18 -04:00
Rejeesh Kutty 02dfd2d2e2 altera/ad_serdes_out- sample transmit order 2016-09-15 10:28:34 -04:00
Rejeesh Kutty 5986f45cba altera/ad_serdes_out- updates 2016-09-15 09:38:11 -04:00