9818bcb601
axi_fifo2f: internal memory low overhead
2014-10-30 11:12:10 -04:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
6470ea91ad
axi_fifo2f: fake version
2014-10-30 11:12:08 -04:00
f9628262aa
axi_dmac: Add xfer_req signal to the streamin AXI source interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
fbce64411e
axi_ad9671: added synchronization interface to altera core
2014-10-29 18:20:26 +02:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9c8fe5f09c
ad7175: Removed unused files
2014-10-28 14:30:41 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
121a416916
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 13:07:55 +03:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
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Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
46d1710539
axi_ad9625: added constraints
2014-10-17 13:57:30 -04:00
37b608f397
axi_ad9144: added constraints
2014-10-17 13:57:09 -04:00
df3915e2b0
ad9625: constraints added
2014-10-17 13:41:56 -04:00
819a3d0802
util_adc_pack: removed latches
2014-10-17 15:40:16 +03:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
206b96d55a
ip: constraint changes
2014-10-15 14:50:58 -04:00
f0b25c39a3
wfifo: added axi stream support
2014-10-15 14:50:56 -04:00
51a15a28b7
axi_fifo2s: added constraints
2014-10-15 14:50:53 -04:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
3d5ef9a8ed
util_dac_unpack: Fix unpack order with 1 channel
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Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:14 +03:00
dd70320b00
axi_spdif: Add missing signals to the regmap read sensitifity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:09 +03:00
e7af6219dd
axi_spdif: Don't use non-static expressions in port assignments
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Fixes a warning from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:05 +03:00
ab5eee42e4
axi_spdif: Set unused signals to 0
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Fixes warnings about undriven signals from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:00 +03:00
0b587e6fb1
axi_i2s: Add missing signals to the regmap read process sensitivity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:56 +03:00
cf2bbf66b7
axi_i2s: Set unused signals to 0
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Fixes warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:51 +03:00
22169c4a9c
axi_dmac: Add default driver values for optional input ports
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This silences warnings from the tools about undriven ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
e7dbdff60c
axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
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The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00
8557073b56
axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:33 +03:00
3e6f553ce3
axi_dmac: Add clock signal spec for m_axis/s_axis bus
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This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:24 +03:00
c2ed80e8bb
axi_dmac: Drive unused signals to 0
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This silences a few warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:49 +03:00
aee95ebe96
axi_dmac: Fix dummy AXI a{r,w}len fields width
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The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:43 +03:00
4f53a69f3c
util_dac_unpack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:37 +03:00
77133fe60a
util_adc_pack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:29 +03:00
3ab0f417b4
util_dac_unpack: Don't use localparam symbols in input/output signals
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When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:19 +03:00
04e4458ee1
util_dac_unpack: Drive unused ports to 0
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Silences a few warnings about undriven ports from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:12 +03:00
61be003017
axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
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This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:41 +03:00
58cbe1813d
scripts/adi_ip: Add helper function to create bus clock and reset interface
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Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:31 +03:00
a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
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It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
Rejeesh Kutty
Lars-Peter Clausen
Adrian Costina
acozma
Istvan Csomortani