cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
76ffb939e5
zc706: ad9625 copy
2014-08-22 11:24:24 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
f3f8414d81
kcu105: changes for ad_iobuf
2014-08-15 15:01:52 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
9438e2a9e0
spdif: constraints file added
2014-08-14 15:09:48 -04:00
1396a215e5
library: local constraints
2014-08-14 15:09:47 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
a54e4edb08
Add xfest14 PMODs project
...
This project has a SPI controller connected to each of the ZED boards PMOD
ports JA, JB, JC, JD pin 1-4. Pin 7-10 are connected to the PS7 general purpose
GPIOs, except for JC where it is connected to the PS7 UART controller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-08-12 10:14:16 +02:00
96969079ce
a5soc: fixes for 14.0 and spi conflicts
2014-08-11 16:46:37 -04:00
a5e3a07375
dma: altera fix id assignments
2014-08-11 16:46:36 -04:00
902d5b0da2
prcfg: Update fmcomms2_pr for ZC706
2014-08-05 17:55:31 +03:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
e9f8c0fb5f
fmcomms5: ZC706 modified constraints for linux build machines
2014-08-01 18:09:55 +03:00
6c6cab0e16
fmcomms2: ZC706 modified constraints for linux build machines
...
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
dfd11cb809
ad9467: register map changes
2014-07-30 15:31:09 -04:00
c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
663588eeaf
daq2/kcu105: working ddr version
2014-07-29 09:15:30 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
...
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
9cdd4107cd
fmcomms5: ZC702: add reset_b and fixed system_top
2014-07-25 15:24:11 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
7bee85423d
c5soc: removed stp/cdf files
2014-07-24 20:53:08 -04:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
...
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
a68f634de9
fmcomms5: Added resetb for the second AD9361
2014-07-24 17:31:30 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
49a77c0413
prcfg: Generate configuration files to *.bin
2014-07-24 09:43:00 +03:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db2386a351
daq2/kcu105: latest mig updates
2014-07-23 16:25:55 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
e3320c43cb
fmcomms2/c5soc: programmer file
2014-07-21 09:06:55 -04:00
9b9e0c6a56
fmcomms2/c5soc: signal tap
2014-07-21 09:06:54 -04:00
65879d621f
daq2: updates for the new hardware
2014-07-21 09:06:53 -04:00
2b6ce1e504
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
2014-07-21 15:10:36 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
085512a738
fmcomms2_pr: Fix the source path for prcfg_setup
2014-07-10 17:54:41 +03:00
95701fbd0e
fmcomms2_pr : PR initial check in
2014-07-10 10:41:48 +03:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
...
Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina