b8f4e1c0aa
updated 9680 hdl files(to resolve a critical warning)
2016-08-10 14:50:31 -04:00
ccf1c56b33
util_upack: Patch up the description of Altera IP
2016-08-08 16:39:56 +03:00
e9ac4a5a0e
util_rfifo: Patch up the description of Altera IP
2016-08-08 16:39:25 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
cba53774ca
axi_dmac: Don't add CDC constraints when all clocks are synchronous
...
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
aece3f5555
axi_ad9680: Update IP core
...
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
a0ae791395
hdl-vivado-2016.2: Update axi_jesd_gt
...
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7988d2c7a2
adi_ip: remove duplicated errored auto address maps & interfaces
2016-07-29 12:32:19 -04:00
4aa506de8d
adxcvr- added a space?
2016-07-29 09:38:08 -04:00
71dad14e0e
axi_adcfifo- disable auto infer mess-up
2016-07-29 09:37:17 -04:00
39ff059ef6
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
d5d61ff518
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
52b544bb66
hdl-vivado-2016.2- auto infer bus interfaces
2016-07-28 13:44:57 -04:00
3384d384d3
hdl-vivado-2016.2- infer bus interfaces separately
2016-07-28 13:44:57 -04:00
c316f0dfea
ad9144- synthesis warnings fix
2016-07-28 13:44:57 -04:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
5c91e41da8
ad9680- sof + sample delineation
2016-07-21 16:09:33 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
75864f0ce5
util_adxcvr- add constraints file
2016-07-21 16:09:33 -04:00
1435c5f7f7
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-21 16:09:33 -04:00
8e04e70791
axi_adxcvr- status output for jesd ip
2016-07-21 16:09:33 -04:00
1f25d7f637
axi_adxcvr- self-disable based on num of lanes
2016-07-21 16:09:33 -04:00
c797a579f1
util_adxcvr- rstdone on usrclk2
2016-07-21 16:09:33 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
3a1ecb7463
ad9162- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
46b00aea2d
util_adc_pack: Delete unused IP core
2016-07-20 14:17:04 +03:00
8902a31ca6
util_dac_unpack: Delete unused IP core
2016-07-20 14:17:04 +03:00
634924246a
axi_jesd_xcvr: Delete Makefile
...
This core is an Altera core only, no need for Makefile.
2016-07-20 14:17:04 +03:00
74c220d79e
make: Update Make files
2016-07-20 14:17:04 +03:00
b9a5bb3549
axi_dacfifo: Optimize the AXI read logic
...
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
Shrutika Redkar
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen
Matthew Fornero