Commit Graph

2888 Commits (b8f4e1c0aa73210fbc93b21f7b543a3b7dbf1db7)

Author SHA1 Message Date
Shrutika Redkar b8f4e1c0aa updated 9680 hdl files(to resolve a critical warning) 2016-08-10 14:50:31 -04:00
Adrian Costina 285059aed0 kcu105: Don't use phy reset automation, as it's not supported for KCU105 2016-08-09 10:19:57 +03:00
Adrian Costina 452d4706d3 kcu105: Update base project to 2015.4.2
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
Rejeesh Kutty c6f4def93d altera- make mmu a make switch 2016-08-08 11:54:51 -04:00
Istvan Csomortani ccf1c56b33 util_upack: Patch up the description of Altera IP 2016-08-08 16:39:56 +03:00
Istvan Csomortani e9ac4a5a0e util_rfifo: Patch up the description of Altera IP 2016-08-08 16:39:25 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani aad8c265bc lib_refactoring: Fix path for CMOS sources 2016-08-08 15:07:54 +03:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Istvan Csomortani 90ac7b7ac9 lib_refactoring: Move all Altera module to library/altera/common
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
Istvan Csomortani cb9af99c5d lib_refactoring: Add ad_mul.v for Altera 2016-08-08 15:06:48 +03:00
Istvan Csomortani f784557895 lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera 2016-08-08 15:06:34 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00
Lars-Peter Clausen 8f61e11a70 pzsdr: ccpci: Add PCIe reset monitor
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 91782989ad pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 418217dd10 pzsdr: Remove LED and button signals from PCIe carrier
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 3cff0fa7dc pzsdr: ccpci: Use PL SPI and GPIO peripherals
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
Adrian Costina 5faf4c4976 cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them 2016-08-05 16:27:52 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty cb23ba8bb7 make- script needs update 2016-08-04 14:17:04 -04:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Rejeesh Kutty 2b7c976be5 xcvr- altera/xilinx split 2016-08-04 13:26:10 -04:00
Rejeesh Kutty ed9e92621c daq2- spi+xcvr address conflict 2016-08-04 10:50:31 -04:00
Lars-Peter Clausen cba53774ca axi_dmac: Don't add CDC constraints when all clocks are synchronous
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
Adrian Costina 999eccc134 daq3: Update A10GX project to Quartus 16.0 2016-08-01 16:19:43 +03:00
Adrian Costina 9a563de8ff daq2: A10GX updated project to Quartus 16.0
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
Adrian Costina 52ae3ddd6c a10gx: Updated common files to 16.0 2016-08-01 15:08:12 +03:00
Adrian Costina aece3f5555 axi_ad9680: Update IP core
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani a0ae791395 hdl-vivado-2016.2: Update axi_jesd_gt
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
Istvan Csomortani af4c43b6e1 hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design 2016-08-01 13:49:12 +03:00
Istvan Csomortani fbe3d75eb0 cosmetics: Delete trailing whitespace characters 2016-08-01 13:46:46 +03:00
Matthew Fornero b99117e686 up_axi: Same cycle BVALID/READY fails on Altera
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
2016-08-01 12:17:10 +03:00
Istvan Csomortani 58b220ba81 ad_tdd_control: Add an on/off switch to the receive datapath
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
Rejeesh Kutty 7988d2c7a2 adi_ip: remove duplicated errored auto address maps & interfaces 2016-07-29 12:32:19 -04:00
Shrutika Redkar 4aa506de8d adxcvr- added a space? 2016-07-29 09:38:08 -04:00
Shrutika Redkar 71dad14e0e axi_adcfifo- disable auto infer mess-up 2016-07-29 09:37:17 -04:00
Shrutika Redkar 9952a94efb hdl-vivado-2016.2- ip version updates 2016-07-28 13:44:57 -04:00
Shrutika Redkar 39ff059ef6 hdl-vivado-2016.2- productivity decimated again! 2016-07-28 13:44:57 -04:00
Shrutika Redkar d5d61ff518 hdl-vivado-2016.2- productivity decimated again! 2016-07-28 13:44:57 -04:00
Shrutika Redkar 52b544bb66 hdl-vivado-2016.2- auto infer bus interfaces 2016-07-28 13:44:57 -04:00
Shrutika Redkar 6ffe59728b hdl-vivado-2016.2- update 2016-07-28 13:44:57 -04:00
Shrutika Redkar 3b2bde2fa1 hdl-vivado-2016.2- min. addr-space requirement 2016-07-28 13:44:57 -04:00
Shrutika Redkar 3384d384d3 hdl-vivado-2016.2- infer bus interfaces separately 2016-07-28 13:44:57 -04:00
Shrutika Redkar c316f0dfea ad9144- synthesis warnings fix 2016-07-28 13:44:57 -04:00
Shrutika Redkar 8a2734b43e up_dac_common- typo- unf register reset 2016-07-28 13:44:57 -04:00
Adrian Costina 08f4ba24d5 usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board 2016-07-28 15:21:38 +03:00
Shrutika Redkar 6ebb32a194 library axi-slave missing protection signal added 2016-07-22 12:54:27 -04:00
Rejeesh Kutty 39a5534e00 hdlmake- updates 2016-07-21 16:10:38 -04:00