Istvan Csomortani
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05469a011c
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ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
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2021-02-04 11:04:32 +02:00 |
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Istvan Csomortani
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738f7af23b
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ad40xx_fmc: SDI delay should be set to 1
In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
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2020-08-13 10:01:16 +03:00 |
Stanca Pop
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fcf7bb035a
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ad40xx: Fix data_width definition
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2020-01-14 15:24:43 +02:00 |
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Stanca Pop
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9497b1cace
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ad40xx: Remove redundant upscaler IP, Add timing constraints
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2020-01-09 11:32:31 +02:00 |
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Istvan Csomortani
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9ab88f1200
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ad40xx: Initial commit
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2019-06-28 11:18:29 +03:00 |