b48401175a
axi_dacfifo: Optimize the AXI write logic
2016-07-20 11:49:06 +03:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
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Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
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Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
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Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
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Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
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DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
e855ef38f4
axi_dacfifo: Initial commit
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AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
Istvan Csomortani