Commit Graph

6294 Commits (b3f3f7c392b0abb00c14d21653ad6f31c994fe9a)

Author SHA1 Message Date
Ionut Podgoreanu b3f3f7c392 docs/regmap: Added the regmap file for the generic TDD controller 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu a3e1e6286b ad9081_fmca_ebz_x_band: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu ef278e1c88 library/axi_tdd: Add generic TDD engine
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 7faefab1be library/scripts: Add SV support for Intel boards
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2022-12-13 16:26:02 +02:00
AndrDragomir 8b9175a80c projects: Fix intermitent timing violation on a10soc
adrv9009, dac_fmc_ebz, ad9081_fmca_ebz, fmcomms8:
Increased PLACEMENT_EFFORT_MULTIPLIER global parameter to 1.2 for increased quality of placement
2022-12-13 14:21:24 +02:00
Sergiu Arpadi f64830364c ad469x: Use axi_pwm_gen; clean-up
Replace axi_pulse_gen with axi_pmw_gen for softare support
considerations. Remove common/config.tcl and update project scripts
accordingly.
2022-11-18 12:54:45 +02:00
PopPaul2021 eb663876d7 axi_ad7768: modified adc_format values and crc_err flag has to be RW1C 2022-11-15 15:43:46 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Filip Gherman 4e8c816d3f adi_board: Connnect phy_en_char_align only for 8B10B encoding
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-11-01 14:24:31 +02:00
Travis F. Collins a07cec4a84 Remove extra FIELD marker in regmap
Fix minor typo in adc regmap which is breaking an external parser.

Signed-off-by: Travis F. Collins <travis.collins@analog.com>
2022-10-19 21:34:37 +03:00
alin724 0620f8425d regmap/adi_regmap_common.txt: Add missing RD_RAW_DATA field 2022-10-19 09:41:38 +03:00
Filip Gherman 56789abf2b docs/regmap: Added the new ADDRESS_HIGH registers to the DMAC regmap
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-10-18 16:59:18 +03:00
Filip Gherman cef4adb81d axi_dmac: Add suport for 64 bit address width
New improvements for the ADI DMAC IP:
1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl)
2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI:
-"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments.
-"Manual mode": Specify the desired dma_width between 32-64 bits.
3)Added two new debug registers that return higher part of the current source/destination address.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-10-18 16:59:18 +03:00
Laszlo Nagy fd0870352b ad9081_fmca_ebz_x_band:zcu102: X band project initial version
HDL project for Stingray: X/Ku Band Phased Array Prototyping System
2022-10-18 09:21:14 +03:00
AndreiGrozav fdb829347a ad9083 based projects: Expose JESD parameters 2022-10-12 17:50:17 +03:00
AndreiGrozav 67a5737fa1 ad9083_vna: Init commit
Compatible with RevB
2022-10-10 17:32:17 +03:00
alin724 28ace647d1 up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module 2022-10-05 14:56:36 +03:00
alin724 5008999bea up_adc_common: Add register data reading/writing functionality 2022-10-05 14:56:36 +03:00
alin724 775a23ebf2 up_adc_channel: Update IPs and adi_regmap_adc definition file to latest up_adc_channel module 2022-10-05 14:27:51 +03:00
alin724 045327c8db common/up_adc_channel: Add raw data reading functionality 2022-10-05 14:27:51 +03:00
laurent-19 1eb5f4985b projects/common: Add build files templates carriers. Modified Quartus Versions
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
	  vck190, vcu118, vcu128, vmk180,
	  zc702, zc706, zcu102, zed

* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
  according to last commit update

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
alin724 a4e052e986 cn0506: Update project's directory name in the README file 2022-10-03 10:30:24 +03:00
Liviu.Iacob 5350baffd0 adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
Liviu.Iacob a95536973f adrv9009/common/adrv9009_bd: Add logic for TX_JESD_L=2 2022-10-03 10:27:33 +03:00
Liviu.Iacob 6a583a8ace projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4 2022-10-03 10:27:15 +03:00
PopPaul2021 56691bd440 projects/cn0501: Updated with axi_ad7768 IP for Coraz7s 2022-09-30 12:56:57 +03:00
PopPaul2021 9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
Iulia Moldovan 880f37555f ad719x_asdz/coraz7s: Initial commit
* Added interrupt on RDYn on GPIO 32

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-28 16:30:42 +03:00
stefan.raus 19c76d1d4f run_tb.sh:don't run xsim if previous commands fail
If 'xvlog' or 'xelab' xilinx commands are failing, exit from
run_tb.sh script without trying to run simulation.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2022-09-28 14:25:21 +03:00
PopPaul2021 8960652c5a
library/jesd204/ad_ip_jesd204_tpl_adc: Added support for PN7 and PN15 (#1019) 2022-09-28 13:07:36 +03:00
Stanca Pop 56290a609d ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00
Stanca Pop d2d32458f4 ad9783_ebz: Match project name with folder name 2022-09-26 15:37:49 +03:00
LIacob106 3e297f54dd projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
2022-09-26 14:26:31 +03:00
stefan.raus 88f48cba61 library/scripts/library.mk: clean files form tb
Update clean command to delete also files generated by simulation,
from 'tb' folders, covering cases for Xsim and ModelSim simulators.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2022-09-26 13:09:21 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
PopPaul2021 542c361e0a
docs/regmap: Added ADI regmap_*.txt files (#1008) 2022-09-21 15:12:35 +03:00
Iulia Moldovan f3f4686759 axi_ltc2387: Update up_adc_common and up_adc_channel instances
* Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
Iulia Moldovan bc94402b91 axi_ltc2387: Make adc_valid to represent the current sample
* Before, adc_valid was for the previous sample. This said that
   at the second rising edge of clk_gate - the first sample is valid,
   which is not true

 * Alongside with the software issue that will be solved, these fixes
   will make the first 2 samples to be with valid data, otherwise the
   user has to always keep in mind that the first 2 ones are invalid

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
Iulia Moldovan 474b8d5bed cn0577/zed: Update xdc to diff_term true. Disable csn in system_top
* Update xdc to use diff_term true instead of diff_term 1
 * Generated xdc using adi_fmc_constr_generator.tcl
 * Make CSN to be inactive
 * Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
laurent-19 6b94259a52 projects/common: Add system_top _project templates
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
AndrDragomir b02f437110 docs: Add common template for evaluation board specific fmc files
Instructions to use the template are found on the first page of the template

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
AndrDragomir 7cde7cd048 projects/scripts: Add fmc constraints generator script
Using the script:
  - make sure that the eval board in use has a common fmc connection file.
  if you created a new one, it should be saved as &project_name_fmc.txt inside
  &project_name/common
  - open a tcl terminal, either inside or outside the project
  - make sure your current directory is &hdl_repo/projects/&project_name/&carrier
  - source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
  - call gen_fmc_constr $parameter_1 $parameter_2:
      - in case of only one fmc port on the carrier call without any parameters
      - if there are two fmc ports on the carrier and you want to use only one,
      the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
      - if there are two fmc ports on the carrier and you want to use both, then
      both parameters should contain an indication
  - the constraints file will be generated in the current directory

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
AndrDragomir 72cf8f9b5d projects/common: Add fmc connection files for every platform 2022-09-20 14:11:08 +03:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Iulia Moldovan b1bf17d574 scripts/check_readme: Change search to be case insensitive
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-01 13:43:25 +03:00
Laszlo Nagy 8905147698 common/tb/ad_pack_tb: Add non random scenario as first test for easier debug 2022-08-25 12:35:59 +03:00
Laszlo Nagy d20e604864 ad9082_fmca_ebz/zcu102: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Laszlo Nagy ee3af4c9c6 axi_jesd204: Cleanup unused parameter 2022-08-25 12:35:42 +03:00