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5263 Commits (b3e1cd2a15d1ec413eab174ba0cec3e6b667b66f)

Author SHA1 Message Date
Istvan Csomortani 59ce663479 util_dec256sinc24b: Fix resets 2019-06-28 11:18:29 +03:00
Istvan Csomortani 6668accc96 ad7405 : Initial commit 
This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 554feaa1af util_pulse_gen: Update ports for all outdated instance 
The new version of util_pulse_gen has different ports and port names.

Update all the instance:
  - AD738x_FMC
  - AD7768EVB
  - ADAQ7980_SDZ
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 7fa620d253 gtm_projects: Update system_top 
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.

Following projects were changed:

  - AD5766_SDZ
  - AD7134_FMC
  - AD7616_SDZ
  - AD77681EVB
  - AD7768EVB
  - ADAQ7980
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 21ce53f765 Revert "Move GTM projects to gtm_projects branch" 
This reverts commit 171093eca4.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani f22f448d4b daq3:vcu118: Delete constraint related to smart connect 
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)

See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
 2019-06-27 13:47:24 +03:00
Istvan Csomortani 65fea6c4c0 ad_ip_jesd204_tpl_dac: Fix up_axi instantiation 
This patch will fix the following warning:

[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
 2019-06-27 13:47:00 +03:00
Laszlo Nagy acf6d618dd util_clkdiv: fix for multiple instances 
Vivado propagates and auto derives the clocks, however if multiple
instances of this components are used the names of the propagated clock
change while the constraint file has fixed name which will match only
the clocks from the first instance letting the second instance of the
clock div without exception.
 2019-06-27 10:33:51 +03:00
Laszlo Nagy fd6a395347 axi_fmcadc5_sync: rename generated spi clock 
Rename the clock so it won't conflict with the main spi clock name.
 2019-06-26 16:10:07 +03:00
AndreiGrozav 1c99fde06b axi_ad9361: Fix Intel interface - technology encoding update 2019-06-25 15:40:51 +03:00
AndreiGrozav 01081c93e8 axi_ad9361: Fix the interface for Intel devices 
Use missing MIMO_ENABLE parameter, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-25 15:40:51 +03:00
Adrian Costina 81bcf9f6fc util_adxcvr: Cleanup whitespaces for GTY4 instantiations 2019-06-25 15:35:49 +03:00
Istvan Csomortani 4896a84c2d ad9739a_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
Istvan Csomortani e0a010c959 ad9625_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
AndreiGrozav 4812f64cdc ad9434: Fix axi_ad9434_dma timing closure 
axi_ad9434_dma/m_dest_axi_aresetn should use sys_dma_resetn
 2019-06-21 09:54:21 +03:00
AndreiGrozav 0a3a99bf83 m2k: Define SPI clock constraint 2019-06-21 09:53:14 +03:00
Sergiu Arpadi 0bbe501764 adrv9009_zu11eg_som: added axi_fan_control 2019-06-14 17:08:38 +03:00
Sergiu Arpadi c159909823 adrv9009_zu11eg_som: added i2s 2019-06-14 17:08:38 +03:00
Adrian Costina 9409df6a6f adrv9009_zu11eg: Initial commit 
Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
 2019-06-14 17:08:38 +03:00
Sergiu Arpadi 369974f2e7 axi_fan_control: updated ip 
fixed tacho evaluation bug; updated fsm;
 2019-06-14 17:08:38 +03:00
Istvan Csomortani 95afc461a6 fmcomms5: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 2e05b70d94 fmcomms11: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani dafc97f43a fmcjesdadc1: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 5266d2ae88 ad6676evb: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 92a0e8eb1e util_adcfifo: Fix SDC cosntraints 2019-06-13 10:59:43 +03:00
Istvan Csomortani 78b14f9803 axi_ad9625: Fix the interface instance 
The axi_ad9625_if does not have a DELAY_REFCLK_FREQUENCY parameter.
 2019-06-13 10:59:43 +03:00
Istvan Csomortani 44a9331471 fmcomms2:fmcomms5: ZCU102 uses 500MHz IO delay clock 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani 993497438b adi_project:adi_project_run: Check if $num_reg exist 2019-06-11 18:13:06 +03:00
Istvan Csomortani 896ea4925d adi_board: Fix ad_mem_hpx_interconnect proc 
Make the lsearch command more robust.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 9072779e41 adrv9371x: Clean out system_db.tcl 2019-06-11 18:13:06 +03:00
Istvan Csomortani de510b45ab base: Add system_processor_rst for all the global clocks 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20c714eccf common: Define three global clock nets 
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
 2019-06-11 18:13:06 +03:00
Istvan Csomortani c4c87c7c7a axi_ad9361: Fix the _hw.tcl script 
This will fix an error introduced by 48d2c9d3 "axi_ad9361: Define a MIMO enabled
parameter"
 2019-06-11 12:39:20 +01:00
Istvan Csomortani 93b2254ff5 axi_ad9361: Fix for 'Define a MIMO enabled parameter' 2019-06-10 14:48:17 +01:00
Istvan Csomortani 48d2c9d36f axi_ad9361: Define a MIMO enabled parameter 
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-10 15:16:47 +03:00
Istvan Csomortani a4a9d0a19d fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz 2019-06-10 11:23:41 +03:00
Istvan Csomortani 119fd0915a fmcomms11: Make the lane remapping after the link layer 2019-06-10 11:23:41 +03:00
Istvan Csomortani 58d55f61db fmcomms11: Add desciption how to swap memory resource for the FIFOs 2019-06-10 11:23:41 +03:00
Istvan Csomortani 5d80aa63b2 fmcomms11: Some cosmetic, no functional change 2019-06-10 11:23:41 +03:00
Istvan Csomortani 94dc848292 fmcomms11: Move the FIFO address variables into system_bd 
These variables can vary in function of the available memory resources
of the FPGA carrier board.
 2019-06-10 11:23:41 +03:00
Istvan Csomortani 559ae69b2b fmcomms11: Fix DAC data path 
Fix the modification 68a5f2.
 2019-06-10 11:23:41 +03:00
Istvan Csomortani d9230fdc5e fmcomms11: Connect DAC fifo bypass to a GPIO 
GPIO[60] can be used to control the bypass line of the
util_dacfifo module.
 2019-06-10 11:23:41 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy 3bf120123b dac_fmc_ebz: update Makefiles 2019-06-06 11:45:05 +03:00
Laszlo Nagy 1541b918d8 dac_fmc_ebz: added README 2019-06-06 11:45:05 +03:00