3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
b8f4e1c0aa
updated 9680 hdl files(to resolve a critical warning)
2016-08-10 14:50:31 -04:00
ccf1c56b33
util_upack: Patch up the description of Altera IP
2016-08-08 16:39:56 +03:00
e9ac4a5a0e
util_rfifo: Patch up the description of Altera IP
2016-08-08 16:39:25 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
cba53774ca
axi_dmac: Don't add CDC constraints when all clocks are synchronous
...
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
aece3f5555
axi_ad9680: Update IP core
...
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
a0ae791395
hdl-vivado-2016.2: Update axi_jesd_gt
...
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7988d2c7a2
adi_ip: remove duplicated errored auto address maps & interfaces
2016-07-29 12:32:19 -04:00
4aa506de8d
adxcvr- added a space?
2016-07-29 09:38:08 -04:00
71dad14e0e
axi_adcfifo- disable auto infer mess-up
2016-07-29 09:37:17 -04:00
39ff059ef6
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
d5d61ff518
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
52b544bb66
hdl-vivado-2016.2- auto infer bus interfaces
2016-07-28 13:44:57 -04:00
3384d384d3
hdl-vivado-2016.2- infer bus interfaces separately
2016-07-28 13:44:57 -04:00
c316f0dfea
ad9144- synthesis warnings fix
2016-07-28 13:44:57 -04:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
5c91e41da8
ad9680- sof + sample delineation
2016-07-21 16:09:33 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
75864f0ce5
util_adxcvr- add constraints file
2016-07-21 16:09:33 -04:00
1435c5f7f7
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-21 16:09:33 -04:00
8e04e70791
axi_adxcvr- status output for jesd ip
2016-07-21 16:09:33 -04:00
1f25d7f637
axi_adxcvr- self-disable based on num of lanes
2016-07-21 16:09:33 -04:00
c797a579f1
util_adxcvr- rstdone on usrclk2
2016-07-21 16:09:33 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
3a1ecb7463
ad9162- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
46b00aea2d
util_adc_pack: Delete unused IP core
2016-07-20 14:17:04 +03:00
8902a31ca6
util_dac_unpack: Delete unused IP core
2016-07-20 14:17:04 +03:00
634924246a
axi_jesd_xcvr: Delete Makefile
...
This core is an Altera core only, no need for Makefile.
2016-07-20 14:17:04 +03:00
74c220d79e
make: Update Make files
2016-07-20 14:17:04 +03:00
b9a5bb3549
axi_dacfifo: Optimize the AXI read logic
...
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
e46990e508
axi_dacfifo: Cosmetic changes
...
Rename a few registers and fix indentation.
2016-07-20 11:49:06 +03:00
b48401175a
axi_dacfifo: Optimize the AXI write logic
2016-07-20 11:49:06 +03:00
74f45cff24
axi-ad9625: fix clock ratio to match sampling clock
2016-07-19 16:21:13 -04:00
1df942b752
rfifo- buffer 1 seg before read
2016-07-12 10:24:22 -04:00
4f0d7bd6eb
util_wfifo: read after write is complete
2016-07-11 09:59:31 -04:00
832efdc99c
hdlmake updates
2016-07-08 13:58:56 -04:00
7a03d44e4e
adxcvr- clock buffers are removed
2016-07-08 13:57:27 -04:00
20ac95b1ec
adxcvr- initial commit
2016-07-08 13:57:27 -04:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
d931b2ee64
ad9162 core verilog files
2016-06-30 10:24:01 -04:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
18e28b01fd
axi_ad7616: Add burst counter to the parallel interface
...
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
cdf01a492e
library/axi_dacfifo: Update the bypass logic
...
The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
def47dd536
interfaces: added xcvr interfaces
2016-06-17 12:00:15 -04:00
36fbf4fc42
util_adxcvr: shared xcvr cores
2016-06-17 11:59:42 -04:00
87cf13b0ef
util_adxcvr- system verilog interfaces
2016-06-16 16:41:43 -04:00
80ce7aeb66
util_adxcvr- updates
2016-06-16 16:40:57 -04:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
...
Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
...
Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
dc45287b14
util_adxcvr- added
2016-06-14 12:19:18 -04:00
c19ed4c8ef
axi_hdmi_tx_core: Fixed embedded sync synchronization signals
2016-06-14 14:30:28 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
27fd5f5bdc
modified prbs7 and prbs15 gereration code
2016-06-13 14:44:03 -04:00
83dd7e91c4
deleted pn23 and pn 31, data width yet to be modified
2016-06-13 14:44:03 -04:00
341b7badee
library/scripts: Remove all autogenerated interface in adi_ip_properties_lite
...
There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
2016-06-10 15:08:05 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
abe837e608
util_rfifo: Set an offset for the write addres
2016-06-02 17:34:29 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
3832f2669e
axi_jesd_xcvr: support tx/rx disable
2016-06-01 13:48:51 -04:00
54f398cc36
ad9371-hw- add dsp slice
2016-06-01 13:48:51 -04:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
...
Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
8caa783f5c
axi_dacfifo: Update the constraints
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
...
Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
...
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
...
AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
7fdaee186c
upack/cpack- qsys ip
2016-05-18 13:24:13 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
e15893444c
upack- fix interface names
2016-05-18 13:24:13 -04:00
285cbc7225
xfifo- fix sdc/xdc names
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
42b0fabd40
axi_hdmi_tx_core: Fixed data path
2016-05-17 14:41:18 +03:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
421c0519f4
util_rfifo- updates
2016-05-16 12:19:38 -04:00
e05204a86d
util_cpack: interface updates
2016-05-16 12:19:38 -04:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
4fbff45e27
util_wfifo- updates
2016-05-16 12:19:38 -04:00
f515885fc4
util_wfifo: altera ip
2016-05-16 12:19:38 -04:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
82d43783f1
util_rfifo: altera ip
2016-05-16 12:19:38 -04:00
31671bf9d5
util_rfifo: constraints
2016-05-16 12:19:38 -04:00
aadb220a3f
zcu102- updates
2016-05-10 15:40:41 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
726ddb6e93
ad_lvds_clk: Fixed assignment mismatched
2016-05-09 10:32:18 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
b36c722ec9
up_hdmi_tx: Discard the standard default values
...
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
68d83def01
axi_hdmi_tx_core: Fixed data path
2016-05-05 13:32:25 +03:00
0d2dc2c62b
axi_hdmi_tx: Fixed data bus width
2016-05-05 13:26:59 +03:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
1aac44b0d9
library: ad_*clk- rst/locked
2016-05-04 13:42:11 -04:00
d82ca5dc3c
library/common- altera variations
2016-05-04 13:42:11 -04:00
b6b68e9ab7
axi_jesd_gt: Split the constraint file
...
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
2016-05-04 19:32:06 +03:00
583bafd17a
axi_ad7616: Add a new register for IF_TYPE
...
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
7ec4c00f9f
axi_ad7616: DMA is always ready
2016-04-29 16:36:33 +03:00
427f85959c
axi_ad7616: Fix the AXI stream interface
2016-04-29 16:34:34 +03:00
33199263e1
axi_ad7616: Delete burst_length register
...
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
d5d7c12f0e
axi_ad7616: Fix the register map
2016-04-25 11:36:39 +03:00
2ccdd426ec
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 11:28:22 +03:00
ad227c1af0
up_axi: Wait more to a valid read acknowledge.
2016-04-25 10:34:17 +03:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
...
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
...
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
896c734792
Revert "foobar"
...
This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
665bfbc991
axi_ad7616: Add M_AXIS_READY_ENABLE parameter
...
m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
...
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
...
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
0d67af370f
util_upack: Fixed problem when dac valid isn't continuous from the DAC
...
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
3d3d1098b4
axi_ad7616: Default DATA_WIDTH is 8 bits
2016-01-28 16:02:01 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
fbb0d368bf
axi_ad7616: Add support for parallel interface
2016-01-28 12:37:22 +02:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
4b962e8d72
spi_engine: The width of the counters depend on the current DATA_WIDTH
2016-01-20 15:44:06 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c865dbf353
axi_ad9680: Fix channel instantiation
2016-01-19 12:49:45 +02:00
df3eefdca1
axi_ad9434: Update constraint file
2016-01-19 12:43:05 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
...
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
4f2b999999
axi_ad9680: Q_OR_I_N is not used in this channel
2016-01-13 16:26:22 +02:00
838b558176
axi_ad9434: Fix adc_status
...
adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
2dcd9136aa
axi_ad6676: Delete confusing comment
2016-01-13 10:20:18 +02:00
c29dd8fad5
axi_ad7616: Fix Makefile
2015-12-21 19:39:58 +02:00
0b55325db9
axi_ad7616: Fix IP packaging script
2015-12-21 19:39:14 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
8ae9de8fba
axi_ad7616: Update core
...
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
4e57170384
spi_engine: Update SPI Engine frame work
...
+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
29a0f27cd1
ad_edge_detect: Add a flop to output, reset is active high
2015-12-14 15:40:29 +02:00
4c2d08a9be
ad9152: altera syntax error
2015-12-11 12:49:00 -05:00
bc93910ee5
ad9152: qsys updates
2015-12-10 16:04:10 -05:00
ff1d98a0c7
ad9144: duplicate include
2015-12-10 16:02:35 -05:00
ce906989d5
ad9152: qsys ip
2015-12-10 09:46:31 -05:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
5cf45b2978
axi_clkgen: Added phase related parameters
2015-12-02 18:50:23 +02:00
36febf8591
Merge branch 'master' into dev
...
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
...
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
df58646925
util_adcfifo: Updated altera interface
2015-11-25 10:20:06 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
...
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
ee0617661e
axi_ad9680: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:45:12 +02:00
f51871c1e4
axi_ad9144: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:44:07 +02:00
76823f95fa
axi_ad9250: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:39:55 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fb269f7a29
util_cpack: Updated altera interfaces
...
- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
e6de2ade78
util_upack: Updated altera interfaces
...
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
c5ff1674c6
axi_dmac: Updated fifo interfaces for easier connectivity
2015-11-24 11:08:28 +02:00
e5d2f5be06
util_upack: Cosmetic changes
2015-11-24 10:55:10 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
bdf9754971
util_tdd_sync: Sync signals output reg is a false path source
2015-11-17 09:42:05 +02:00
9ba8c059ce
ad_tdd_sync: Fix reset value of the pulse_counter
2015-11-13 18:31:24 +02:00
d6eae81bc1
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 18:14:21 +02:00
3c27b3a4c5
ad_lvds_in: Add single ended option
2015-11-13 12:13:09 +02:00
952a491f59
axi_ad7616: Add spi engine to the core
2015-11-12 16:12:16 +02:00
b17fec689e
ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
...
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
a290611c09
util_tdd_sync: Initial commit
...
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
e4927887fd
spi_engine_offload: Add sync_bits to the IP files list
2015-11-10 13:35:15 +02:00
229cd079b9
spi_engine: Fix to support multiple SDI lines
2015-11-10 13:34:29 +02:00
64d1948ea0
axi_ad7616: Initial commit
2015-11-10 13:32:56 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
839e76996f
axi_gpreg: added constraints
2015-11-05 11:28:37 -05:00
482b740229
axi_gpreg: add buffer enable
2015-11-05 11:28:35 -05:00
66d4f8fd58
util_gtlb: output receive/transmit clocks
2015-11-05 11:28:34 -05:00
28bfeb442c
util_gtlb- syntax error fixes
2015-11-05 11:28:31 -05:00
6d28a92b5b
util_adcfifo: Added altera initial constraints file
2015-11-04 13:34:52 +02:00
e8b84b3662
axi_dmac: Updated axis destination / source ports for altera component
2015-11-04 13:33:41 +02:00
de53a61902
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
...
Added altera component
2015-11-04 13:31:50 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
ad1cef1441
axi_gpreg: compile fixes
2015-11-03 14:29:00 -05:00
c8019b69fd
axi_gpreg- added
2015-11-03 14:28:59 -05:00
88f247a1de
util_gtlb: use gpio
2015-11-03 14:28:57 -05:00
cf58110a98
Merge branch 'dev' into dev_ad7616
2015-11-03 14:07:48 +02:00
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
...
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
a147acd791
spi_engine: Add support for multiple SDI lines.
...
By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
6fb56079ee
library/util_gtlb: Add Makefile
2015-10-16 13:58:01 +03:00
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
...
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
44568f1f64
util_jesd_gt: bad idea, it is needed for ipi
2015-10-15 11:13:08 -04:00
a6ff1b13fc
util_jesd_gt- remove unused parameters
2015-10-15 10:46:07 -04:00
c9a5057b93
library/prcfg : Split data bus to channels
...
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
a753d506c5
axi_mc_controller: Removed channels, as no data needs to be streamed to DMA
2015-10-09 13:54:03 +03:00
694dbd3259
axi_mc_controller: Updated constraints
2015-10-09 13:53:13 +03:00
7c3646e863
axi_mc_current_monitor: Removed stub channel
2015-10-09 13:52:14 +03:00
99e6240126
axi_mc_current_monitor: Updated constraints
2015-10-09 13:51:15 +03:00
d19d9c8fbc
axi_mc_speed: Corrected maximum number of channels
2015-10-09 13:50:25 +03:00
ce01185348
axi_mc_speed: Updated constraints
2015-10-09 13:50:08 +03:00
96d363849e
ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block
2015-10-09 13:43:14 +03:00
df8ac2e726
axi_ad9671: Updated constraints
2015-10-09 13:15:55 +03:00
03b225a802
axi_ad9671: Fixed synchronization mechanism
2015-10-09 13:15:12 +03:00
8321d5a4fb
util_dacfifo: Update read out method
...
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
1ebd38c514
util_dacfifo: Update read out method
...
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 16:50:36 +03:00
cd9754afbe
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
f3ffd5a63f
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
2b894bc13e
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
5c3f90a676
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
ba70c7a4ea
ad9144- ip updates
2015-09-30 11:37:10 -04:00
54fcf06eed
ad9152- ip updates
2015-09-30 11:34:09 -04:00
81a1c21553
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 12:33:46 +03:00
97a9ecfc9a
axi_hdmi_rx: Update constraint file and fix reset line
2015-09-29 18:49:30 +03:00
b765be568f
up_gt_channel: Delete the register, which stores transceiver type
...
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
cffb2e6226
up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
2015-09-29 14:19:52 +03:00
a0ac0e912b
up/ad_gt_common/channel: Cosmetic changes
2015-09-29 14:16:24 +03:00
dff6c0df01
axi_ad9652: Updated with the latest constraints
2015-09-28 11:29:07 +03:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
...
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
884973fdbb
util_dacfifo: Cosmetic changes
2015-09-25 17:41:44 +03:00
2816812e0a
axi_ad9625: Updated constraints and added adc reset port
2015-09-25 17:16:31 +03:00
37a4e976d6
axi_ad6676: Updated constraints
2015-09-25 17:02:42 +03:00
061f468fb1
axi_ad9250: Update library
...
- added adc reset port
- addded common constraints
2015-09-24 19:10:19 +03:00
ebaebc54f7
axi_ad9680: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:29 +03:00
9ad59c58db
axi_ad9234: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:18 +03:00
0b08250261
axi_ad9152: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:08 +03:00
892755c084
axi_ad9144: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:18:48 +03:00
5e082be963
axi_ad9680: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:14:01 +03:00
edb94ada8b
axi_ad9234: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:13:20 +03:00
d45f49c062
axi_ad9152: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:12:36 +03:00
0a4f43efea
axi_ad9144: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:11:29 +03:00
900db3d8ed
util_wfifo: Fix reset related timing violation
...
The memory instance reset connected to ground, rather than connect to dout_rstn.
2015-09-23 16:36:33 +03:00
516c59523d
util_wfifo: Cosmetic changes.
2015-09-23 16:36:31 +03:00
568333bbfc
axi_dmac: Fix typo on ./bd/bd.tcl
2015-09-23 15:51:50 +03:00
aa608e3907
axi_ad9467: Update constraints
2015-09-23 14:26:57 +03:00
0411ad2386
axi_ad9434: Update constraints
2015-09-23 14:26:55 +03:00
ab8256cf92
ad_tdd_control: Redesign the state machine to prevent timing failure.
2015-09-22 10:33:50 +03:00
cd93beb10f
util_axis_fifo: Remove m_axis_addr_next output from the address modules
...
Remove m_axis_addr_next output from the address modules since it is no
longer used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
5c22e622de
axi_dmac: Fix width for dest response FIFO
...
The width of the dest response FIFO is 1 bit not 3 bits.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
cfd57fc462
axi_dmac: Drive unused interface output ports with const value
...
Drive all output pins of the disabled interfaces with a constant value.
This avoids warnings from the tools about not driven output ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
fed14cf613
axi_dmac: Mark unused output ports explicitly as unconnected
...
Mark all unused output ports explicitly as explicitly. This makes it clear
that they are left unconnected on purpose and avoids warnings from the
tools about unconnected ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
a7f4b11624
axi_dmac: Beautify IPI GUI
...
Group the axi_dmac parameters by function and provide a human readable name
for the IPI GUI. This makes it easier to understand what parameter does
what when using the IPI GUI to configure the core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
5b5a4707d2
axi_dmac: Add validation values to IPI package
...
Add validation values for the different configuration parameters. This
enables the tools to check whether the configured value is valid and avoids
accidental misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
104e49d515
axi_dmac: Remove unused address bits on AXI-Lite bus
...
The address width for the AXI-Lite configuration bus for the core is only
14 bit. Remove the upper unused bits from the public interface.
This allows infrastructure code to know about this and it might be able to
perform optimizations of the interconnect based on this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
89ceae3757
axi_dmac: Move m_axi_src interface clock and reset next to other signals
...
Move the clock and reset signals of the m_axi_src interface next to the
other signals in the module definition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:24 +02:00
5aa11feb48
axi_dmac: Change BRAM REGCEB constraint to set_false_path
...
According to the documentation when using a BRAM block in SDP mode the
REGCEB pin is not used and should be connected to GND. The tools though
when inferring a BRAM connect REGCEB to the same signal REGCEA. This causes
issues with timing verification since the REGCEB pin is associated with the
write clock whereas the REGCEA pin is associated with the read clock.
Until this is fixed in the tools mark all paths to the REGCEB pin as false
paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:22 +02:00
4c51224696
axi_dmac: Configure AXI master bus properties according to core configuration
...
Configure the maximum burst size as well as the maximum number of active
requests on the AXI master interfaces according to the core configuration.
This allows connected slaves to know what kind of requests to expect and
allows them to configure themselves accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:19 +02:00
12fc6d1672
axi_dmac: Indicate that the core does not issue narrow AXI bursts
...
The axi_dmac core does not issue narrow AXI bursts. Indicate this by
setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master
interfaces.
This allows connected slaves to know that they will not receive narrow
bursts, which allows them to disable support for it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:18 +02:00
5f307f862f
axi_dmac: Use sane defaults for the AXI protocol type
...
The axi_dmac core generates requests which are both AXI3 and AXI4
compliant. This means it is possible to connect it to both a AXI3 or AXI4
slave port without needing a AXI protocol converter. Unfortunately it is
not possible to declare a port as both AXI3 and AXI4 compliant, so the core
has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which
allow to configure the protocol type of the corresponding AXI master
interface. Currently the default is always AXI4.
But when being used on ZYNQ it is most likely that the AXI master interface
of the DMAC core ends up being connected to the AXI3, so change the default
to AXI3 if the core is instantiated in a ZYNQ design.
The default can still be overwritten by explicitly setting the
configuration property.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:17 +02:00
f079b2193a
axi_dmac: Add support for auto-detecting asynchronous clock configuration
...
Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.
Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.
It is still possible to automatically overwrite the configuration
parameters by hand if necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
19f7d8500c
adi_ip.tcl: Add support for adding bd files to a core
...
bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:14 +02:00
39320ef48b
axi_dmac: Fix source pause signal
...
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:13 +02:00
91bb54467b
axi_dmac: Generate per core instance constraint file
...
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
0f5f21eec2
adi_ip.tcl: Add helper function to add TTCL files to a core
...
Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:10 +02:00
46808c4c41
util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO
2015-09-16 18:55:47 +03:00
6804f3377a
axi_ad9643: Updated core with latest constraints
2015-09-16 15:49:13 +03:00
5347c058df
axi_ad9122: Updated core with latest constraints
2015-09-16 15:48:33 +03:00
884f45c81d
common library: Registered dc_filter and iq_correction coefficients
2015-09-16 14:24:18 +03:00
052860cbc3
axi_dmac: Fix source pause signal
...
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-16 11:02:08 +02:00
5af371db6b
axi_dmac: Generate per core instance constraint file
...
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:54:33 +02:00
522f30ce21
adi_ip.tcl: Add helper function to add TTCL files to a core
...
Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:00:56 +02:00
7c896ba5f8
axi_ad9361: Fixed constraints definition
2015-09-14 18:20:30 +03:00
67ffeb18e8
axi_ad9739a: Updated core with latest constraints
2015-09-11 14:04:33 +03:00
e33403816c
axi_ad9265: Updated core with latest constraints
2015-09-11 11:26:28 +03:00
5bc16159fa
ad_tdd_sync: The resync will reset all the control lines
2015-09-10 11:28:36 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
...
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
6acb350ee5
axi_dmac: Update for axi_dmac_constr.xdc
...
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
381ffd43c1
gtlb- remove pn test-reset
2015-09-08 13:52:33 -04:00
9bef9742b7
jesd_gt- cosmetic changes
2015-09-03 16:16:24 -04:00
84ced344d9
gtlb- up-sync make w1c
2015-09-03 16:16:22 -04:00
e0b5044aa3
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
2a09257f38
pzslb- updates - wip
2015-08-31 15:41:28 -04:00
c1b01517f8
util_gtlb: added
2015-08-31 15:41:22 -04:00
1e5afdd535
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
6cf7eb5ad4
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
4554eb03b0
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
704385a8dc
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
a33c08725b
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
88f806f584
ad9361- alt io matching
2015-08-27 11:55:24 -04:00
74e72021f7
ad9361- ensm through dev-if
2015-08-27 11:41:53 -04:00
664ef017bb
ad9361- ensm through dev-if
2015-08-27 11:41:52 -04:00
29b0ec0378
ad9361- ensm through dev-if
2015-08-27 11:41:51 -04:00
d82d37c23f
ad9361- ensm through dev-if
2015-08-27 11:41:49 -04:00
2259b6cbf7
ad9361- ensm through dev-if
2015-08-27 11:41:48 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
c56b534ec0
dacfifo- remove interfaces
2015-08-27 11:18:00 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
f3410a7db1
xpack- remove useless interfaces
2015-08-26 14:12:14 -04:00
b0d22d323a
ad9361- axi-clock definitions
2015-08-26 14:11:43 -04:00
4655af7bf6
2015.2 updates
2015-08-26 11:33:44 -04:00
18f688514b
2015.2 updates
2015-08-26 11:33:37 -04:00
7780b3a3a2
2015.2 updates
2015-08-26 11:33:27 -04:00
7b858bc5ad
Revert commit 6b99ce
...
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
386cc74ab4
util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
...
Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
c2ea667a01
library/IPI: Set ASSOCIATED_RESET parameter for AXI interface
...
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
2015-08-25 09:36:42 +03:00
0c3f110bff
library: Fix broken parameters
...
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
2015-08-25 09:19:47 +03:00
da315eb6c0
library: 2015.2 updates
...
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
111287604b
xcvr- remove status constraint
2015-08-20 13:54:15 -04:00
0d482e7ef6
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:25:01 +02:00
37c14e782d
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:12:10 +02:00
d59ec3b36d
unused ip cores
2015-08-20 11:37:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
d67a4a3088
axi_ad9434: Removed duplicate parameter
2015-08-20 18:19:59 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
0d1d8310fd
axi_dmac: Parameter changes
...
Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 16:06:26 +03:00
82e703df23
parameter changes
2015-08-20 08:53:51 -04:00
db18924f8a
library/scripts: Fix ipx::get_file_groups process call
...
ipx::get_file_groups does not work, if there is specified just a [<pattern>] for its argument. Need to use a -filter to get proper result.
2015-08-20 10:56:37 +03:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
6ab28ccb0c
axi-jesd-xcvr- parameter changes
2015-08-19 14:55:11 -04:00
28eb09b4d5
axi-jesd-xcvr- parameter changes
2015-08-19 14:55:08 -04:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
5e252f17b9
cpack- ad_rst port addition
2015-08-19 13:26:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
f7f902c7b4
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
549801cf2e
library: Delete unused IP cores
...
Delete IP "controllerperipheralhdladi_pcore" and "ip_pid_controller"
2015-08-19 12:24:10 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
...
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
8e536ad8d1
axi_ad9361: Update Make file
2015-08-19 12:14:03 +03:00
e64baad54a
axi_dmac: Fix a bug occuring on transfers < one beat
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:26 +02:00
114d48d4e1
axi_dmac: Fix a bug occuring on transfers < one beat
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:06 +02:00
f5de5ca487
usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism
2015-08-19 10:12:24 +03:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
c22d1c044b
axi_jesd_gt-- gt interfaces
2015-08-14 15:34:49 -04:00
890f743f1a
util_jesd_gt-- gt interfaces
2015-08-14 15:34:30 -04:00
6eb0b5eeda
scripts-- add interface procedures
2015-08-14 15:33:58 -04:00
2345be2237
interfaces-- transceiver cores
2015-08-14 15:33:36 -04:00
af87b65788
interfaces_ip: added
2015-08-14 11:24:27 -04:00
ebecfde64c
axi_hdmi_tx: common constraints & async resets
2015-08-13 13:03:51 -04:00
a6f6c81795
axi_jesd_gt- gt lane split
2015-08-13 13:03:51 -04:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
2b8e1bdb74
adi_ip- parse file list for constraints
2015-08-13 13:03:51 -04:00
3615c9cad7
axi_jesd_gt- bug fixes
2015-08-13 13:03:51 -04:00
44d51e665d
util_jesd_gt- port type fix
2015-08-13 13:03:51 -04:00
8697b0a8d6
axi_jesd_gt- ip script changes
2015-08-13 13:03:51 -04:00
e265ca9ea7
util_jesd_gt- ip tcl changes
2015-08-13 13:03:51 -04:00
a108ca9309
util_jesd_gt- updates
2015-08-13 13:03:51 -04:00
a4076424e0
util_jesd_gt- added
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
3ed350efbc
axi_jesd_gt- split up
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ce26373e8a
axi_ad9671: updated constraints to apply in all cases
2015-08-13 11:53:15 +03:00
0379279bd4
axi_ad9671: Fixed rx_sof pin name
2015-08-12 10:20:09 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
f59058dd8a
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-06 15:17:19 +03:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
6104061d19
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-04 13:46:15 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
ed6bdf66bd
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-29 11:59:17 +03:00
05ba125694
ad_tdd_control: Connect the reset to all the flops
2015-07-29 11:56:40 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
d5d7a24483
util_cpack: Added reset interface
2015-07-28 11:00:54 +03:00
623c3dc333
axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports
2015-07-24 16:41:41 +03:00
caca364c61
ad9652- iqcor iqsel changes
2015-07-24 08:35:13 -04:00
144b8f7383
ad9643- iqcor iqsel changes
2015-07-24 08:34:52 -04:00
43946a54a4
axi_dmac: Added C_FIFO_SIZE parameter
2015-07-24 15:30:10 +03:00
649297a0e3
ad_iqcor- changes
2015-07-23 16:20:46 -04:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
3d1ffe7bd2
util_cpack: Added reset interface
2015-07-23 17:01:53 +03:00
f7d28e0944
axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them
2015-07-23 17:01:02 +03:00
41e9a34886
axi_ad9250: Changed Altera interface specification to be compatible with upack
2015-07-23 16:59:57 +03:00
901bcb2c06
dma- constraints modifications
2015-07-22 12:46:06 -04:00
3d7afb8fc5
jesd-xcvr: constraints modifications
2015-07-22 12:46:06 -04:00
6352884398
jesd-xcvr: common align function
2015-07-22 12:46:06 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
ac39329046
axi_spdif_rx: Fix the pl330_dma control path
...
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
3a4581a8df
axi-xcvr: removed xcvr compoents
2015-07-21 10:56:04 -04:00
264f9ffbfc
ip_alt- avalon/reset definitions
2015-07-21 10:55:13 -04:00
3101045109
qsys- library group
2015-07-17 10:07:15 -04:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
31584cf27e
ad9680- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
60c344cea6
ad9144- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
29c6e90d38
util_bsplit: remove avalon streaming interface
2015-07-15 09:44:57 -04:00
af898de818
axi_jesd_xcvr: remove avalon streaming interface
2015-07-15 09:44:56 -04:00
ea57e49da7
axi_ad9250: remove avalon streaming interface
2015-07-15 09:44:54 -04:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
8d6c39d307
ad9680- remove avalon streaming
2015-07-13 10:03:38 -04:00
c69e36314c
ad9144- remove avalon streaming
2015-07-13 10:03:16 -04:00
9d95ddc620
reset and clock additions
2015-07-09 14:29:08 -04:00
d6d263341e
signal tap needs another method
2015-07-08 15:47:47 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
b4eb7465ed
library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit
2015-07-08 10:48:58 +03:00
23428ac48b
transceiver constraints for sysref
2015-07-07 15:25:36 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
b106b8a8f4
library/axi_jesd_xcvr: updates
2015-07-06 13:51:55 -04:00
c67ca682a4
hw.tcl- added
2015-07-06 13:51:55 -04:00
1cfe6fe792
axi_jesd_xcvr: initial commit
2015-07-06 13:51:55 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
7376218e01
axi_spdif_rx: Initial commit
...
NOT tested.
2015-07-03 17:46:45 +03:00
896888d495
axi_mc_current_monitor: updated ad7401 driver to send unsigned data
2015-07-02 14:23:19 +03:00
04527f8b18
axi_mc_current_monitor: updated ad7401 driver to send unsigned data
2015-07-02 14:21:26 +03:00
3c6d19d33d
axi_hdmi_tx_es: Drop strange port initializers
...
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
26b0ff9853
axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
...
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6aee17da83
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
35988b2dba
axi_hdmi_rx: Fix packed 422 mode
...
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
fa15f8d0b5
axi_hdmi_rx: Add full range support to the TPM
...
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
fcb841d3e5
axi_hdmi_rx: Move TPM to its own module
...
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
ab6ea2c824
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
a2a4f3402c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
4744fca18e
axi_ad9361: Bring up the tdd_enable bit
...
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 14:59:32 +03:00
a497dcabb5
axi_ad9361: Bring up the tdd_enable bit
...
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
23034965c8
axi_hdmi_tx_es: Drop strange port initializers
...
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cb03152f1f
axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
...
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
bc4bb111d9
axi_hdmi_rx: Fix packed 422 mode
...
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
13c122f1a1
axi_hdmi_rx: Add full range support to the TPM
...
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
4503402eef
axi_hdmi_rx: Move TPM to its own module
...
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
...
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
caabb9444a
axi_mc_speed: Removed unneded constraints
2015-06-29 16:53:39 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
...
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
c9d976d4f7
axi_hdmi_rx: Fix alignment issue on packed formats
...
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:47:15 +03:00
1abd1a46b1
axi_hdmi_rx: Fix synchronization issues
2015-06-24 12:47:02 +03:00
c0dd80ccee
axi_hdmi_rx: Fix alignment issue on packed formats
...
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
281a47c117
bsplit- altera version, avalon needs a clock
2015-06-24 05:31:08 -04:00
f4a1a5817c
jesd-align: allow sof pass through -- qsys can only do 1 src-dest
2015-06-24 05:31:06 -04:00
e1b1e1bc2c
ad9250- update to use alt ip interface script
2015-06-24 05:31:04 -04:00
00bc48bc24
axi_hdmi_rx: Fix synchronization issues
2015-06-24 11:03:39 +03:00
4e30a5b0bf
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:29:23 +03:00
c9e152e500
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:28:02 +03:00
3e5a5504a7
library/jesd-align- remove signaltap interface
2015-06-19 14:33:03 -04:00
af2ffbe0a0
library/cpack- add signaltap
2015-06-19 14:33:02 -04:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
8a52631189
libary: util_jesd_align- signal tap interface
2015-06-19 14:32:57 -04:00
7e08ff0422
library: added util_jesd_xmit
2015-06-19 14:32:56 -04:00
ad743c8403
axi_ad9434: This IP core does not have 'data underflow' port
2015-06-18 16:51:42 +03:00
d137811952
util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
...
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
04eb998ff1
axi_jesd_gt: constraints
2015-06-10 14:29:06 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
df0eaad1e2
gt: constraints
2015-06-10 11:38:15 -04:00
d6163bea5e
axi_jesd_gt: Fixed constraints
2015-06-10 10:56:22 +03:00
5e4f572092
axi_ad9122: Fixed constraints
2015-06-10 10:56:03 +03:00
8a1f4bf5f6
ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports
2015-06-09 14:21:12 +03:00
a598e1c614
axi_ad9265: Set default driver value for overflow and underflow ports
2015-06-08 17:50:23 +03:00
ccf887f0ba
axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports
2015-06-08 17:48:41 +03:00
ded0dd5dbe
axi_ad9122: fixed constraints, removed unneded drp reset
2015-06-08 17:45:14 +03:00
4b08df9ed6
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
c926daca3a
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
ce60056cd5
wfifo: async reset for cpu side
2015-06-05 12:44:04 -04:00
ab1f9bed10
wfifo: remove srl from sync registers
2015-06-05 12:44:04 -04:00
da8915296b
pack: ip scripts
2015-06-05 09:20:08 -04:00
6338dfd8b7
ad9361: ip defaults & rst output
2015-06-05 09:19:39 -04:00
cb0324c2b1
wfifo: multi-channel option
2015-06-05 09:19:05 -04:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e02273781f
ad_rst- non lpm version
2015-06-04 10:53:12 -04:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
2b5abf74d7
util_upack: Show upack_valid only if the channel is activated
2015-06-02 11:36:06 +03:00
297e885981
library- drp moved to up-clock domain
2015-06-01 14:52:52 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
d7b68c39ef
altera- sdc
2015-06-01 10:59:59 -04:00
2a0bdbebf2
altera- sdc
2015-06-01 10:59:58 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
dc2eeebf2f
upack: gen-name
2015-05-21 14:06:12 -04:00
5c6340e927
dmac: clock-typo
2015-05-21 14:06:11 -04:00
e05ff26406
ad9144: ddata-typo
2015-05-21 14:06:09 -04:00
8d78217f7b
ad9680: missing prot. ports
2015-05-21 14:06:08 -04:00
4c6a3afc88
ad9144: missing prot. ports
2015-05-21 14:06:06 -04:00
a059290cf5
Remove axi_ad7175
...
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
...
Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
d43ba44d0f
Add util_sigma_delta_spi peripheral
...
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
e6b58e8a20
Add SPI Engine framework
...
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.
Currently included are four components:
* SPI Engine execution module: The excution module is responsible for
handling the low-level physical interface SPI logic.
* SPI Engine AXI interface module: The AXI interface module allows
memory mapped acccess to a SPI bus control stream and can be used to
implement a software driver that controls the SPI bus.
* SPI Engine offload module: The offload module allows to store a
predefined SPI Engine command and data stream which will be send out
when a external trigger signal is asserted.
* SPI Engine interconnect module: The interconnect module allows to
combine multiple control streams into a single stream giving multiple
control modules access to a execution module.
For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
a5b452cc27
Add axi_generic_adc core
...
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
033713ccb5
Add cordic demodulator module
...
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
cefbe3a0ff
scripts/adi_ip.tcl: Add option to specify reset interface direction
...
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
5ac7ebb8a3
axi_mc_*: Removed delay pins from up_adc_common
2015-05-21 14:03:58 +03:00
465f7dff88
library/util_jesd_align -added
2015-05-20 15:38:43 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
da0409b5a6
library- qsys components
2015-05-20 11:51:50 -04:00
9b425736ac
library: altera ip modifications
2015-05-20 10:41:21 -04:00
d48d3f4aa3
scripts/ip-alt- added
2015-05-20 09:11:18 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
4fb1be0672
ad9680: delay changes
2015-05-19 12:53:56 -04:00
af7afd7366
ad9671: delay changes
2015-05-19 12:53:56 -04:00
09a05fe9d8
ad9652: delay changes
2015-05-19 12:53:56 -04:00
13156593f8
ad9643: delay changes
2015-05-19 12:53:56 -04:00
c8d3c04a05
ad9625: delay changes
2015-05-19 12:53:56 -04:00
f53204f9f9
ad9467: delay changes
2015-05-19 12:53:56 -04:00
fe0ceb2530
delay-cntrl updates
2015-05-18 15:23:10 -04:00
304a202d67
delay-cntrl updates
2015-05-18 14:57:05 -04:00
2e257db109
delay-cntrl updates
2015-05-18 14:53:24 -04:00
0877c252ad
delay-cntrl changes
2015-05-18 14:28:20 -04:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2c1719095d
util_axis_resize: Changed _ip.tcl format to the standard format
2015-05-18 17:25:07 +03:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
c9c05e21c2
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 16:34:06 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
a1d680ee6b
ad9680- add hw tcl
2015-05-12 15:06:42 -04:00
833a3de6b5
ad9680- add hw tcl
2015-05-12 15:06:39 -04:00
48c769d431
ad9144- add hw tcl
2015-05-12 14:40:38 -04:00
553f89f59d
ad9144- add hw tcl
2015-05-12 14:39:57 -04:00
4553de3ffa
ad9361- align hold
2015-05-11 11:55:01 -04:00
9934cce5d2
util_dacfifo: Add CDC logic for dma_lastaddr register.
2015-05-11 12:20:46 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
...
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
14e23b106c
axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx
2015-05-08 17:43:10 +03:00
12ed393d39
ad9361- framing modifications
2015-05-07 15:13:18 -04:00
a68539edf1
ad9361- framing modifications
2015-05-07 15:13:17 -04:00
176a4a4b76
ad9361: add ddr-edgesel
2015-05-06 16:58:50 -04:00
a8534a9c02
ad9361: add ddr-edgesel
2015-05-06 16:58:49 -04:00
32f7e98afd
ad9361: add ddr-edgesel
2015-05-06 16:58:47 -04:00
670850183b
axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied
2015-05-06 18:53:19 +03:00
a7c96fdac8
util_dacfifo: General clean up of the IO, input/output data has the same width
2015-05-06 16:32:44 +03:00
0613dca0b7
axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module
2015-05-06 16:10:28 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
65af205d6b
axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
...
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
233cc111d2
util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
2015-05-05 23:33:13 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
707b285669
prcfg: bb def
2015-05-04 10:24:13 -04:00
be32715ab3
axi_adcfifo: Updated constraints
2015-04-30 14:23:24 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
463c4d4d28
util_wfifo: Added constraint for the resetn path
2015-04-30 12:05:02 +03:00
392ba31a07
axi_hdmi_rx: Updated constraints
2015-04-30 12:04:15 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
c36186f75a
axi_ad9643: Added adc_rst output
2015-04-28 14:52:24 +03:00
8ee3f64a65
axi_ad9265: Added adc_rst output
2015-04-28 14:51:14 +03:00
67c581cef8
util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain
2015-04-28 14:50:00 +03:00
1ad87aa27c
util_wfifo: Added constraints
2015-04-27 11:19:56 +03:00
81d4e1d9b1
axi_clkgen: Updated constraints
2015-04-27 11:19:15 +03:00
d950f5ffcd
axi_ad9122: Updated constraints
2015-04-27 11:18:52 +03:00
9fba4cb2ef
util_dacfifo: Add support for Slave AXI stream interface.
...
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
3a02998e9a
axi_ad9152/axi_ad9152_ip.tcl: Fix typo
...
axi_ad9152_constr.v -> axi_ad9152_constr.xdc
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
a9924e6401
util_gmii_to_rgmii: Added constraints
2015-04-23 16:53:57 +03:00
bd06bae8c2
library: Modified the adi_ip.tcl script
...
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
d42c0bc431
axi_jesd_gt : Added CDC and reset constraints
2015-04-23 11:03:51 +03:00
1b4e6bdc80
axi_mc_speed : Added CDC and reset constraints
2015-04-23 10:50:49 +03:00
6d28d217f1
axi_mc_current_monitor: Added CDC and reset constraints
2015-04-23 10:49:43 +03:00
d0b2d531bc
axi_mc_constroller: Added CDC and reset constraints
2015-04-23 10:47:35 +03:00
d0571a912f
axi_hdmi_tx: Added CDC and reset constraints
2015-04-23 10:46:04 +03:00
cc7d9f9d54
axi_clkgen: Added CDC and reset constraints
2015-04-23 10:44:37 +03:00
d1558df625
axi_ad9739a: Added CDC and reset constraints
2015-04-23 10:42:27 +03:00
97dc7ea004
axi_ad9680: Added CDC and reset constraints
2015-04-23 10:40:41 +03:00
f1f8c14813
axi_ad9671: Added CDC and reset constraints
2015-04-23 10:39:11 +03:00
744a15a0ba
axi_ad9652: Added CDC and reset constraints
2015-04-23 10:37:15 +03:00
eca616a3ae
axi_ad9643: Added CDC and reset constraints
2015-04-23 10:35:12 +03:00
a62415b0ab
axi_ad9625: Added CDC and reset constraints
2015-04-23 10:33:51 +03:00
b4a09daf89
axi_ad9467: Added CDC and reset constraints
2015-04-23 10:30:33 +03:00
ac79c65b81
axi_ad9434: Added CDC and reset constraints
2015-04-23 10:28:46 +03:00
a6cb6b7672
axi_ad9265: Added CDC and reset constraints
2015-04-23 10:27:29 +03:00
08f19d489f
axi_ad9250: Added CDC and reset constraints
2015-04-23 10:25:19 +03:00
734fdab326
axi_ad9234: Added CDC and reset constraints
2015-04-23 10:23:22 +03:00
09f05cf8e9
axi_ad9152: Added CDC and reset constraints
2015-04-23 10:21:52 +03:00
3526145992
axi_ad9144: Added CDC and reset constraints
2015-04-23 10:19:43 +03:00
e7ce2b200d
axi_ad9122: Added CDC and reset constraints
2015-04-23 10:17:53 +03:00
691c54e0dd
axi_ad6676: Added CDC and reset constraints
2015-04-23 10:16:29 +03:00
7b073aaec1
axi_dmac: Always generate local interrupt for asynchronous interfaces
...
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.
While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
5edcc753ec
axi_dmac: Ignore timing on more debug signals
...
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
ae808ba942
axi_dmac: Fix block ram constraint
...
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 19:56:42 +02:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
...
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
988bf60747
axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only
...
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.
Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 10:15:02 +02:00
996d0fe8a4
axi_hdmi_tx: Only mark HDMI clocks asynchronous to each other
...
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.
The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:18:51 +02:00
e3b834ea02
axi_ad9361: Add CDC constraints
...
Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
0dc3bb8905
axi_dmac: Fix src_reponse_fifo control signals
...
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
42a9da0659
axi_dmac: Only apply CDC constraints if clocks are asynchronous
...
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.
Also add -quiet parameters to avoid generating warning if the constraints
could not be added.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
9c249d25ab
axi_dmac: Make internal resets active high
...
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
fd2f5836f0
axi_dmac: Fixed type in the altera hardware file
2015-04-17 14:59:47 +03:00
dfc22fc7de
axi_i2s_adi: Overhaul CDC
...
* Generate a separate synchronous reset for the data clock domain.
* Add missing stage to toggle synchronizers.
* Give a common prefix to CDC elements and add the proper constraints to the
XDC file
* Remove some unnecessary resets
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
8289262807
axi_spdif_tx: CDC overhaul
...
Use common prefix for CDC elements and add the proper constraints to the XDC
file. And add a missing stage to the toggle synchronizers.
Also drop a some unnecessary resets.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
9183f2287a
axi_spdif_tx: Use adi_ip_constraints
...
Use adi_ip_constraints to add the constraints file instead of open-coding
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
bfd84edc46
adi_ip.tcl: adi_ip_constraints: Add support for VHDL projects
...
Match both xilinx_verilogsynthesis and xilinx_vhdlsynthesis when getting the
file group.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
7c97e192f2
dma_fifo: Simplify FIFO WE condition
...
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample. Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
34aa0cfda2
Partially revert "axi_dmac: Set proper constraints"
...
This partially reverts commit f51c941c2d
2015-04-16 10:01:19 +02:00
f13666cd81
ad9361: axi_dmac_constr: Fix typo
2015-04-16 10:01:19 +02:00
f51c941c2d
axi_dmac: Set proper constraints
...
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.
For single-bit synchronizers use set_false_path to not constraint the path
at at all.
For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.
For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:26 +02:00
b14721b8ae
library: Use common prefix for CDC signal names
...
Use a common naming scheme for CDC signals to make it easier to create
constraints for them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
c9206433b5
adi_ip.tcl: Allow to specify processing order for adi_ip_constraints
...
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:15 +02:00
24df683a2a
axi_dmac: Disable src_response_fifo for now
...
The result of the src_response_fifo is currently not used so disable it for
now.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:12 +02:00
4062aa2860
util_axis_fifo: Fix reset signal
...
Some of the synchronizers were using the wrong reset signal, fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:11 +02:00
762fa3290b
util_axis_fifo: Add room and level outputs
...
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.
Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:09 +02:00
ae4e7a0c37
util_axis_fifo: Add option to disable registered output
...
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:08 +02:00
f6594e276e
Bring back AXIS FIFO as a separate module
...
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
8fc4b0630e
util_axis_resize: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:04 +02:00
cb98e3e151
adcfifo: unused process
2015-04-13 13:31:50 -04:00
95e41e50a6
axi_dmac: Make all clocks asynchronous
2015-04-11 12:04:55 +03:00
7d22399860
util_axis_resize: Fixed makefile
2015-04-09 18:06:56 +03:00
e9bd4b3512
axi_dmac: Updated altera core dependency, changed fifo files location
2015-04-09 17:58:21 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
b7d8e38c94
util_dacfifo: General update
...
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
668b8bda62
util_axis_resize: Add support for specifying the endianness
...
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
f1eb1c6064
util_axis_resize: Add support for non power-of-two ratios
...
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
b6458f9aab
axi_dmac: Move axi_repack block to its own module
...
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
8a47d0f94b
adi_ip: Add helper function to add dependency to a IP core
...
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:52:41 +02:00
88abf98bd6
adi_env.tcl: Make default ad_hdl_dir path detection more robust
...
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 14:43:56 +02:00
bdaad46704
axi_dmac: Remove up_write signal
...
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
98609527e3
axi_i2s: Add I2S interface definition
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
86e6f67d4b
util_i2c_mixer: Add I2C interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
fa696adc98
util_dac_unpack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
978f41cbe8
util_adc_pack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
6ba0667939
axi_dmac: Add fifo_wr/fifo_rd interfaces
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
c82b186610
Add interface definitions for the fifo_rd and fifo_wr interfaces
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
11cc18be79
adi_ip.tcl: Initialize ip_repo_paths
...
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
d17cd22ef1
adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
...
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.
This makes the function more flexible and e.g. allows to handle buses from other vendors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
0d0c15df98
axi_adcfifo: fix file names
2015-04-07 16:40:52 -04:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
922ea7fb34
util_sync_reset: removed
2015-04-07 16:28:05 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
e73e563a02
util_adcfifo_axi: removed
2015-04-07 16:16:51 -04:00
712becd57f
adcfifo: axi version
2015-04-07 16:16:17 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
dfaa6f6571
fifo2s: removed
2015-04-07 16:01:36 -04:00
3c316efbc5
fifo2dac: removed
2015-04-07 16:01:21 -04:00
69cadd46ed
adcfifo_axi: added
2015-04-07 16:00:47 -04:00
056d6bbf40
dacfifo: added
2015-04-07 15:55:29 -04:00
99c124e708
fifo2f: removed
2015-04-07 15:53:22 -04:00
9098e3ebca
fifo: removed
2015-04-07 15:52:31 -04:00
86a70b3054
adcfifo: added
2015-04-07 15:43:02 -04:00
7224ca1f0c
dma: moved
2015-04-07 15:35:47 -04:00
9fa3131858
axi_fifo2dac: Initial commit
...
BRAM fifo for high speed DACs
2015-04-07 17:46:36 +03:00
de2c3764d6
util_upack: Updated IP, added upack_valid and dma_xfer_in/dac_xfer_out ports.
2015-04-07 16:55:25 +03:00
8af60576cd
dma: constraints
2015-04-06 13:38:31 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
ba2e635918
makefile: added
2015-04-01 16:28:20 -04:00
2f41aebaa9
makefile: added
2015-04-01 16:28:19 -04:00
a5f937a96d
makefile: added
2015-04-01 16:28:18 -04:00
8b09fedae9
makefile: added
2015-04-01 16:28:16 -04:00
64601272da
makefile: added
2015-04-01 16:28:15 -04:00
e0c7ad802a
makefile: added
2015-04-01 16:28:14 -04:00
b0db485e0d
makefile: added
2015-04-01 16:28:13 -04:00
a10c7a4245
makefile: added
2015-04-01 16:28:11 -04:00
afb7115b2f
makefile: added
2015-04-01 16:28:10 -04:00
90298816e4
makefile: added
2015-04-01 16:28:09 -04:00
96c81013ac
makefile: added
2015-04-01 16:28:08 -04:00
20280fecbe
makefile: added
2015-04-01 16:28:06 -04:00
8ec8c966b1
makefile: added
2015-04-01 16:28:05 -04:00
63efcbf4ca
makefile: added
2015-04-01 16:28:04 -04:00
1d3129a600
makefile: added
2015-04-01 16:28:03 -04:00
00411a53da
makefile: added
2015-04-01 16:28:01 -04:00
15c25ac45b
makefile: added
2015-04-01 16:28:00 -04:00
a63d4ae65c
makefile: added
2015-04-01 16:27:59 -04:00
4222b35292
makefile: added
2015-04-01 16:27:58 -04:00
9ced8643c6
makefile: added
2015-04-01 16:27:56 -04:00
109a38e0e8
makefile: added
2015-04-01 16:27:55 -04:00
871460016d
makefile: added
2015-04-01 16:27:54 -04:00
c0a4c6e046
makefile: added
2015-04-01 16:27:52 -04:00
5a5ffb7745
makefile: added
2015-04-01 16:27:51 -04:00
54ee0a0273
makefile: added
2015-04-01 16:27:50 -04:00
3dbbb4e5bb
makefile: added
2015-04-01 16:27:49 -04:00
566e8d7fd3
makefile: added
2015-04-01 16:27:47 -04:00
500f71af2f
makefile: added
2015-04-01 16:27:46 -04:00
4e7538fc8b
makefile: added
2015-04-01 16:27:45 -04:00
13a40af558
makefile: added
2015-04-01 16:27:44 -04:00
36b629dab1
makefile: added
2015-04-01 16:27:42 -04:00
856220e9e9
makefile: added
2015-04-01 16:27:41 -04:00
43f5025ecd
makefile: added
2015-04-01 16:27:40 -04:00
5b18d12c23
makefile: added
2015-04-01 16:27:39 -04:00
f20ab424f7
makefile: added
2015-04-01 16:27:37 -04:00
4ab17615ce
makefile: added
2015-04-01 16:27:36 -04:00
234d4ae7f3
makefile: added
2015-04-01 16:27:35 -04:00
55406b7a61
makefile: added
2015-04-01 16:27:34 -04:00
6cff03390c
makefile: added
2015-04-01 16:27:32 -04:00
a97fc603f8
makefile: added
2015-04-01 16:27:31 -04:00
35205c43a1
makefile: added
2015-04-01 16:27:30 -04:00
1b5737968a
makefile: added
2015-04-01 16:27:29 -04:00
6ac43fe516
makefile: added
2015-04-01 16:27:27 -04:00
c2e626d0b6
axi_hdmi_tx: es split
2015-04-01 15:08:24 -04:00
3bca324c33
hdmi_rx: 64bit + es split
2015-04-01 14:25:55 -04:00
56165b89f7
hdmi_rx: 64bit + es split
2015-04-01 14:25:49 -04:00
01d0b495ec
hdmi_rx: 64bit + es split
2015-04-01 14:25:45 -04:00
d4763fe356
hdmi_rx: 64bit + es split
2015-04-01 14:25:41 -04:00
11d94b736a
util_gmii_to_rgmii: Added to dev branch
2015-04-01 17:22:49 +03:00
ae26c7817e
Remove util_sync_reset
...
The util_sync_reset peripheral hasn't been used in a while and will not be
used in new projects. So remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:46:41 +02:00
fd7a423f74
axi_dmac: Reset data stream resize blocks when disabled
...
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:18:34 +02:00
2d7bae2ba6
axi_mc_controller: Added delay module
2015-04-01 12:22:20 +03:00
de12184038
axi_mc_speed: Updated for motor control revision 2
2015-04-01 11:43:22 +03:00
d5fa0071bd
axi_mc_current_monitor: Updated for motor control revision 2
2015-04-01 11:42:28 +03:00
6ee66df41e
axi_mc_controller: Updated for motor control revision 2
2015-04-01 11:41:33 +03:00
4b1d9fc86b
axi_dmac: Modified in order to avoid vivado crash
2015-04-01 11:39:25 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
0e1a60e8b7
axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface.
2015-03-26 12:20:32 +02:00
6ee9b3a1e2
util_wfifo: Fixed reset
2015-03-25 15:34:21 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
ffe410b2dd
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
09bb184505
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
f92011f72d
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
5d50d38c66
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8f5551718e
axi_fifo2s: false paths on up_xfer_toggle
2015-03-19 16:33:14 -04:00
7e15fd9e5b
util_upack: Fixed ip
2015-03-19 16:22:12 +02:00
bc04e5a4ce
axi_i2s_adi: Fixed pins directions
2015-03-12 17:22:52 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
6995f63134
Add version check to adi_ip.tcl too.
2015-03-05 11:55:09 +02:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
65bda6505e
axi_dmac: Correctly handle shutdown for the request splitter
...
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
731e1c0996
axi_dmac: Use internal enable signal for the request generator
...
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
582ea06918
axi_dmac: request_generator: Stop generating requests when disabled
...
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
aa594e15f3
axi_dmac: fifo_inf: Handle overflow and underflow correctly
...
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
6edcaa478a
adi_ip: updates for 2014.4
2015-02-19 11:11:39 -05:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
518d842af9
upack: initial commit
2015-02-06 15:15:33 -05:00
d02c21b426
util_pmod_adc: General update
...
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
96899313d8
axi_dmac: Fix constraint
...
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
b10ba49425
axi_dmac: Fix constraint related issue
...
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
d5bd485624
axi_dmac: Fix eot issue under 2014.4
...
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
5a1819ed6e
fifo2s: qualify last with valid
2015-01-15 15:42:10 -05:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
63633a0fa5
ad9739a: constraints
2015-01-08 10:25:45 -05:00
ed73a9d1cf
ad9739a: updated to ad9739a
2015-01-08 10:25:15 -05:00
14df46c193
library: Initial commit of axi_hdmi_rx ip core
...
Status unknown, NOT tested.
2015-01-08 16:58:56 +02:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
...
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
ad4b4f64d0
ad9739a: ad9122 copy
2015-01-07 15:36:02 -05:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
b65bcab8d6
up_clkgen: reading typo
2015-01-07 13:58:43 -05:00
5f93c859b5
util_rfifo: renamed ports to make vivado happy
2015-01-06 16:16:42 -05:00
8056574bae
util_wfifo: renamed ports to make vivado happy
2015-01-06 16:16:25 -05:00
0291bb3bf7
util_rfifo: port name fixes & doc.
2015-01-06 16:15:51 -05:00
36b041ccc0
util_wfifo: port name fixes & doc.
2015-01-06 16:15:42 -05:00
ee0912eb6a
ad9361: make 2t2r external for mw
2015-01-05 10:54:23 -05:00
c3529f112f
up_gt: move status to up clock
2014-12-19 13:00:27 +02:00
f4774d6f98
fifo2s: false path typo on source signals
2014-12-19 13:00:13 +02:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
16f64a75d6
fifo2s: false path typo on source signals
2014-12-15 13:00:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
c4152627f0
plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
...
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
2014-12-09 13:59:19 +02:00
19732d89fb
plddr3: Fix the adc_dwr pulse width
...
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
2014-12-09 13:51:00 +02:00
6aad2fbbb2
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 10:19:03 +02:00
6f8c259961
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 09:56:14 +02:00
a70d27c094
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:53:11 +02:00
26f58914e2
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:53:06 +02:00
7e8e1e4fd0
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:52:59 +02:00
ea1a50c985
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:46:20 +02:00
0d2888a5a6
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:45:37 +02:00
21591dc485
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:43:59 +02:00
6197563506
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
afddc45ba4
library/ccat: initial commit
2014-11-25 12:59:51 -05:00
196e8b119c
library/bsplit: initial commit
2014-11-25 12:59:50 -05:00
403f8c0631
util_cpack: ipi doesn't like local params
2014-11-21 15:32:13 -05:00
3b500bafcc
util_cpack: add port controls on ipi
2014-11-21 15:32:12 -05:00
5ca2944b70
library/util_cpack: initial checkin
2014-11-21 15:32:10 -05:00
42874bfe81
prcfg_library: Major update
...
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
2014-11-18 10:05:52 +02:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
6dd1226696
axi_ad9643: Fixed constraint file
2014-11-17 12:12:09 +02:00
8831d9dbd7
axi_ad9122: fixed constraint file
2014-11-17 12:11:20 +02:00
2744d0cb37
util_wfifo: Update to implement flip flops
2014-11-17 12:10:21 +02:00
41ffc66c26
fifo2s: removed m interface
2014-11-13 15:00:03 -05:00
8761db438e
axi_fifo2f: common interface with fifo2s
2014-11-12 15:15:32 -05:00
925e966eb6
axi_fifo2s: fifo full replaced with ready
2014-11-12 14:43:47 -05:00
5fc4f1b000
axi_fifo2s: buswidth fix
2014-11-12 14:43:46 -05:00
d204a7c2b7
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:44 -05:00
e7cec7171e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:43 -05:00
4381f20a6a
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:42 -05:00
9f2dbad539
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:41 -05:00
e683b5868e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:40 -05:00
81b4cd532d
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:38 -05:00
888ab888d2
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:37 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
bf62665c56
prcfg_qpsk: Add Simulink model
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Matlab version used: R2014a, HDL Coder 3.3
2014-11-12 15:44:38 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
cb15567a56
ad6676: added
2014-11-10 13:36:07 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
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This reverts commit b254380338
2014-11-06 12:16:52 +02:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
d69ccebbde
ad9234: full 16bit samples
2014-11-05 11:59:08 -05:00
403fe1b373
wfifo: read only if ready is asserted
2014-10-31 13:05:17 -04:00
38652b1c3e
axi_ad9643: Added constraint file
2014-10-31 17:57:47 +02:00
3e9ce71d21
axi_ad9122: Added constraint file
2014-10-31 17:56:56 +02:00
d596d71285
prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
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This fix the wrong symbol mapping issue.
2014-10-31 12:14:52 +02:00
eb520b1f75
prcfg_qpsk: Major update
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Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
2014-10-31 12:10:59 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
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Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
9818bcb601
axi_fifo2f: internal memory low overhead
2014-10-30 11:12:10 -04:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
6470ea91ad
axi_fifo2f: fake version
2014-10-30 11:12:08 -04:00
f9628262aa
axi_dmac: Add xfer_req signal to the streamin AXI source interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
fbce64411e
axi_ad9671: added synchronization interface to altera core
2014-10-29 18:20:26 +02:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9c8fe5f09c
ad7175: Removed unused files
2014-10-28 14:30:41 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
121a416916
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 13:07:55 +03:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
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Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
46d1710539
axi_ad9625: added constraints
2014-10-17 13:57:30 -04:00
37b608f397
axi_ad9144: added constraints
2014-10-17 13:57:09 -04:00
df3915e2b0
ad9625: constraints added
2014-10-17 13:41:56 -04:00
819a3d0802
util_adc_pack: removed latches
2014-10-17 15:40:16 +03:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
206b96d55a
ip: constraint changes
2014-10-15 14:50:58 -04:00
f0b25c39a3
wfifo: added axi stream support
2014-10-15 14:50:56 -04:00
51a15a28b7
axi_fifo2s: added constraints
2014-10-15 14:50:53 -04:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
3d5ef9a8ed
util_dac_unpack: Fix unpack order with 1 channel
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Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:14 +03:00
dd70320b00
axi_spdif: Add missing signals to the regmap read sensitifity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:09 +03:00
e7af6219dd
axi_spdif: Don't use non-static expressions in port assignments
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Fixes a warning from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:05 +03:00
ab5eee42e4
axi_spdif: Set unused signals to 0
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Fixes warnings about undriven signals from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:00 +03:00
0b587e6fb1
axi_i2s: Add missing signals to the regmap read process sensitivity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:56 +03:00
cf2bbf66b7
axi_i2s: Set unused signals to 0
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Fixes warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:51 +03:00
22169c4a9c
axi_dmac: Add default driver values for optional input ports
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This silences warnings from the tools about undriven ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
e7dbdff60c
axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
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The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00
8557073b56
axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:33 +03:00
3e6f553ce3
axi_dmac: Add clock signal spec for m_axis/s_axis bus
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This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:24 +03:00
c2ed80e8bb
axi_dmac: Drive unused signals to 0
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This silences a few warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:49 +03:00
aee95ebe96
axi_dmac: Fix dummy AXI a{r,w}len fields width
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The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:43 +03:00
4f53a69f3c
util_dac_unpack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:37 +03:00
77133fe60a
util_adc_pack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:29 +03:00
3ab0f417b4
util_dac_unpack: Don't use localparam symbols in input/output signals
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When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:19 +03:00
04e4458ee1
util_dac_unpack: Drive unused ports to 0
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Silences a few warnings about undriven ports from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:12 +03:00
61be003017
axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
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This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:41 +03:00
58cbe1813d
scripts/adi_ip: Add helper function to create bus clock and reset interface
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Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:31 +03:00
a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
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It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
5565cf8fad
axi_ad9467: Independent read/write update
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Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
a436153a48
axi_ad9434: Independent read/write update
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Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
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No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
6a09a1ed19
ad9434: Fix the processor read interface
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Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
2014-09-25 16:51:58 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
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All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
d5f4991e26
ad9434: Merge the ad9434_if interface data outputs into one single bus
2014-09-25 16:45:12 +03:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
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Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
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A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
e528ee0b52
axi_ad9234: axi_ad9680 copy
2014-09-22 11:27:15 -04:00
de0edc2083
axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active
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Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-16 21:02:05 +02:00
c927e90ee1
axi_dmac/axi_fifo: Add missing file
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
17a993032b
util_dac_unpack: Make number of channels and channel width configurable
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Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.
So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:04 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
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By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
36422f0454
axi_dmac: Remove Altera toplevel wrapper
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We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:28:14 +02:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
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Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
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Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
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Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
0da7b6eaa1
axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24
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This is the same as the default value in axi_dmac.v
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:07:35 +02:00
a4b9b1254a
axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
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We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
0966366514
motor_control: Updated the FOC IP
2014-09-08 15:52:18 +03:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
acde4f2c9a
axi_dmac: Added fix to work with motor_control
2014-09-03 12:10:34 +03:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
a773cc4992
usdrx1: updated project
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ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
cf660c126d
util_adc_pack: Fixed problems when working in 4 channels mode
2014-08-29 13:51:40 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
272874f6ad
ad9652: pnmon fixes
2014-08-27 10:44:38 -04:00
31002c404c
util_adc_pack: Added parameters for configuring data width and number of channels
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Valid values for the number of channels is 4 or 8
Valid values for datawidth is 16 or 32
2014-08-27 14:47:57 +03:00
58fa0776c9
axi_dmac: Added patch to fix issue on altera systems
2014-08-26 16:24:34 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
9438e2a9e0
spdif: constraints file added
2014-08-14 15:09:48 -04:00
1396a215e5
library: local constraints
2014-08-14 15:09:47 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
a5e3a07375
dma: altera fix id assignments
2014-08-11 16:46:36 -04:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
dfd11cb809
ad9467: register map changes
2014-07-30 15:31:09 -04:00
c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
...
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db1c931736
ad9625_plddr: PL DDR3 fixes
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- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
...
Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
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Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
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Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
f3b20fd148
axi_ad9625: register map updates
2014-07-03 11:19:31 -04:00
1a78ac453e
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-07-02 15:39:42 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e4ce00f7fb
axi_ad9680: register map changes
2014-07-02 12:50:09 -04:00
7e5748374d
prcfg_lib: Fixed prbs generator for QPSK
2014-07-02 18:14:35 +03:00
8eb7a55797
prcfg_lib: Fixed the gpio status merge logic
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The previous logic did not passed implementation.
2014-07-02 18:09:48 +03:00
9089877c70
prcfg_lib: Fixed the sine tone generator for BIST
2014-07-02 18:00:43 +03:00
8a2b29cdbe
axi_damc: Add xfer_req to the FIFO source interface
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The xfer_req signal will be high if DMA core the is expecting data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-07-02 16:05:16 +02:00
31abd07613
axi_ad9144: register map changes
2014-07-01 21:43:04 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
4afe6c24e9
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-06-25 15:26:21 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
4fdb3cfc4a
ad9250: register map updates
2014-06-25 15:23:57 -04:00
4f5d163fcc
Merge branch 'master' into devel
2014-06-25 13:07:12 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
4877df9bec
axi_fifo2s: make read dead slow
2014-06-25 09:20:57 -04:00
985ace533e
ad9361: remove unused modules
2014-06-24 14:26:40 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
89961c8dd7
prcfg_lib: Update the PR libraries
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+ Flop the control nets too inside the adc/dac module
+ Flop the gpio_out in prcfg_top
2014-06-13 20:35:35 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
87bec07a22
ad9625: added multi-sync support
2014-06-12 15:45:34 -04:00
5189d200e7
axi_fifo2s: linux fix on interfaces
2014-06-12 15:30:13 -04:00
3e5990366e
axi_ad9625: initial release
2014-06-09 16:39:08 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
ea22d29862
prcfg: Initial check in of PR modules
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Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
fa998a406b
dma: parameter fix
2014-04-24 15:50:16 -04:00
314ec3d343
altera-9250/dma: make id width generic
2014-04-24 14:54:19 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
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Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
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We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
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Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
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It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
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Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
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Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
...
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
e85153b5dd
altera hal version
2014-04-01 21:12:11 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
25f416e46f
dds output is reset if disabled
2014-03-31 10:01:49 -04:00
d3d26e1220
lower the address space requirements
2014-03-26 11:03:45 -04:00
9b4539b7c2
axi_dmac: Add option to configure the FIFO size
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-26 12:51:35 +01:00
ca7a70650d
axi_dmac: Delay up_ack by one clock cycle
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The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 14:35:52 +01:00
b3657b77cb
util_sync_reset: Fix polarity of the sync_resetn signal
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 13:03:12 +01:00
a230e6505a
axi_dmac: Add option to configure AXI standard
2014-03-25 12:47:27 +01:00
d0e26899a4
Add util_sync_reset helper module
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This helper module can be used to make sure that a reset signal is de-asserted
synchronously to a clock signal. This is e.g. required by the AXI spec.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-24 22:43:01 +01:00
ef960a29c7
altera files
2014-03-24 13:27:27 -04:00
551319a670
Modified data mover to improve timing
2014-03-20 18:22:18 +02:00
e373b85954
axi_dmac: Fix Vivado warnings
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 20:59:13 +01:00
29d590c951
axi_dmac: response_generator: Do not generate responses during ID sync
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During an ID sync the request_id might increment, we should not generate a
response in this case. Since the ID sync only happens when the core is disabled
check that the core is enabled before generating a response.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 19:12:13 +01:00
df1c4f0786
axi_dmac: data_mover: Improve timing
...
The pending_burst signal and the expression id != request_id are almost
identical. pending_burst goes high with a delay of one clock cycle, but the
important thing is that it goes low on the same clock cycle as the expression.
By using pending_burst here instead of 'id != request_id' we can reduce the
fanout of the 'id' register and improve the timing of the core.
2014-03-18 19:06:26 +01:00
522a222d3a
axi_dmac: Fix default value for DMA type
...
Vivado doesn't handle the case where we use symbolic constants for the default
value properly, so update this to use plain integers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-17 13:20:49 +01:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
f02ba999ae
axi_dmac: Add support for DMA bus widths other than 64 bit
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There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-13 13:20:10 +01:00
fd14607da5
mult instances: consistent naming style
2014-03-12 15:42:47 -04:00
64a89ff66b
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-12 15:36:00 -04:00
7fc5b8ecd9
common: use dsp slice for multiply modules
2014-03-12 15:35:21 -04:00
ba484999b3
Fix default value of $ad_hdl_dir and $ad_phdl_dir
2014-03-12 18:18:47 +02:00
cda3cb3280
removed misc stuff
2014-03-12 11:02:53 -04:00
92aaf0bd51
FMCOMMS1: Updated projects and axi_ad9643 core
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ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.
ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing
AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
2014-03-12 16:23:41 +02:00
580808e146
axi_ad9361: added
2014-03-11 20:01:55 -04:00
a76d6c4686
library/axi_ad9122,axi_ad9643: added
2014-03-11 12:13:25 -04:00
e1f23e7d49
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-11 09:58:34 -04:00
0817973cc0
library: removed xilinx dc filter and dds
2014-03-10 14:52:48 -04:00
f9dfd944c9
library/util_fifo: updates for read side
2014-03-10 14:48:14 -04:00
a6d747411e
util_wfifo: ip cleanup
2014-03-10 11:21:20 -04:00
bb0431d3e8
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:50 -04:00
d6256e9e29
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:16 -04:00
8326022adc
axi_dmac: address_generator: Fix disable race condition
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If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:40:49 +01:00
6da9c65a08
axi_dmac: Add support for zero latency transfer switching
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Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:39:20 +01:00
23a62a92b2
up_adc_common: dma bus width is 0x8 (constant)
2014-03-06 19:22:19 -05:00
831c19ea84
Added axi_dmac, axi_fifo and misc files in library
2014-03-06 18:16:02 +02:00
63bd2b870a
pointers to directories
2014-02-28 16:58:30 -05:00
ff5021b1a8
pointers to directories
2014-02-28 16:57:19 -05:00
f7c9368abc
initial checkin
2014-02-28 14:26:22 -05:00
Rejeesh Kutty
Shrutika Redkar
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen
Matthew Fornero
AndreiGrozav
István Csomortáni
Dragos Bogdan
Paul Cercueil
acozma
ATofan
U-ANALOG\ACostina
Istvan Csomortani