Commit Graph

1443 Commits (b206f8f37a8fc18c6539adae7335596df08c998c)

Author SHA1 Message Date
Lars-Peter Clausen 547dc04857 axi_ad9963: Sign extend ADC data when processing is bypassed
Match the behaviour of the processing data path and sign extend the output
data to 16-bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen a0e30a2211 util_axis_fifo: Improve clock gating of registers and BRAM
Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 72cdd846b0 axi_ad9963: Allow to disable the IDELAYs on the ADC data path
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 09ffe42603 ad_lvds_in: Allow to disable IDELAY
The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 45f87b46c2 ad_lvds_in: Use "SAME_EDGE" mode
Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then
the negative data is delayed by an additional clock cycle. This is the same
behaviour as using the IDDR in SAME_EDGE mode.

Switching to SAME_EDGE mode removes extra pipelining registers while
maintaining the same behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0e2b47e517 axi_adc_trigger: Temporarily disable trigger reporting in register map
The current implementation doesn't quite work right when the interface
clock is slower than the trigger clock and also causes timing issues.
Disable it temporarily until a proper CDC transfer is implemented.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina be6fa287fa axi_dac_interpolate: Make dac_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 7227e74444 axi_adc_decimate: Make adc_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 094872619d axi_ad9963: Separated adc/dac clock and reset 2017-04-18 12:17:39 +02:00
Adrian Costina 9f8fd5c922 axi_ad9963: updated tx path
- removed pll for power saving, added serdes circuitry instead
2017-04-18 12:17:39 +02:00
Adrian Costina fc7f2ef11b ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data 2017-04-18 12:17:39 +02:00
Adrian Costina 166a4c53d5 ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 71469490c6 Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that
they use the same clock. Yet when connecting a single read-only and a
single write-only interface to a Xilinx AXI interconnect it instantiates
arbitration logic between the two interfaces. This is dead logic and
unnecessarily utilizes the FPGAs resources.

Introduce a new helper module that takes a read-only and a write-only AXI
interface and combines them into a single read-write interface. The only
restriction here is that all three interfaces need to use the same clock.

This module is useful for systems which feature a read DMA and a write DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 957730c421 up_dac_common: Allow to disable GPIO registers
Not all peripherals use the GPIO register settings, but the registers still
take up a fair amount of space in the register map. Add options to allow to
disable them when not needed. This helps to reduce the utilization for
peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0ae0da488b up_adc_common: Allow to disable GPIO and START_CODE registers
Not all peripherals use the GPIO and START_CODE register settings, but the
registers still take up a fair amount of space in the register map. Add
options to allow to disable them when not needed. This helps to reduce the
utilization for peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:38 +02:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani 3f0633aadc spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:57:22 +02:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c637d848bb util_clkdiv: constraints should be applied LATE for this core 2017-04-03 18:14:29 +03:00
Istvan Csomortani e0efbe210e constraints: constraint files should be specified at adi_ip_files 2017-04-03 18:12:28 +03:00
Rejeesh Kutty 2f023437b4 adi_ip- remove adi_ip_constraints 2017-04-02 10:42:51 -04:00
Rejeesh Kutty d916697263 adi_ip- a little rearrangement 2017-04-01 09:04:35 -04:00
Istvan Csomortani fd56b5a6d3 axi_ad9122: Update constraint files 2017-03-31 10:13:42 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Lars-Peter Clausen 495d2f3056 axi_dmac: Propagate awlen/arlen width through the core
Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 17:19:38 +02:00
Istvan Csomortani ebfed4b24b ad_axi_ip_constr.xdc: Delete file 2017-03-30 16:16:02 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Lars-Peter Clausen 983e56d72c ad9963: Remove localparams from module parameter list
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
Istvan Csomortani 1d448f0013 adi_ip: Set up SCOPE_TO_REF for xdc and save the core 2017-03-29 18:40:24 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Istvan Csomortani 335fef0f42 ad_axi_ip_constr: Split up this constraint file into separate files
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
Rejeesh Kutty 2419b3626b ad9684- fix sdc typo 2017-03-23 12:49:44 -04:00
Rejeesh Kutty ae0f4672b2 daq1/a10gx- fix project to compile 2017-03-23 09:46:40 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty c277b39796 arradio/c5soc- critical warnings fix 2017-03-20 12:14:13 -04:00
Adrian Costina cd0701513a axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path 2017-03-14 18:00:42 +02:00
Lars-Peter Clausen 3c7f73a880 axi_dmac: Fix dummy port enablement dependency
It seems that in the latest version a constant of "0" is no longer a valid
enablement dependency and "false" has be used instead.

Not setting the enablement dependency correctly results in the AXI port to
be assumed to be read-write rather than just read or write. This will
generate unnecessary logic for example in interconnects to which the DMA
controller is connected.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-14 16:03:25 +01:00
Adrian Costina d7edd71aef axi_logic_analyzer: Triggering changes on valid data 2017-03-14 15:25:00 +02:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
Rejeesh Kutty b0e88eb5ff axi_ad9361- add receive init delay 2017-03-13 16:28:24 -04:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
Adrian Costina ce6b0cc7f3 util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
This removes the added DC component that was introduced by the previous rounding mode
2017-03-09 16:33:17 +02:00
Adrian Costina eb946b54cc util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input 2017-03-08 14:29:26 +02:00
Istvan Csomortani 660dddf1e8 util_dacfifo: Define constraints for bypass 2017-03-07 16:14:46 +02:00
Rejeesh Kutty 7559d23873 util_dacfifo/constraints- false paths for bypass 2017-03-06 10:33:07 -05:00
Istvan Csomortani 7478777d8d axi_dacfifo: Match the ports with util_dacfifo 2017-03-03 18:46:16 +02:00