Laszlo Nagy
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e332409610
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ad9081_fmca_ebz: Make TPL width overwritable
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2022-08-25 12:35:42 +03:00 |
Iacob_Liviu
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482f0489a3
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scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
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2022-08-08 13:52:54 +03:00 |
David Winter
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b9554a9a5a
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ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
Signed-off-by: David Winter <david.winter@analog.com>
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2021-09-30 14:45:54 +03:00 |
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Laszlo Nagy
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75b965e87f
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ad9081_fmca_ebz/zcu102: Enable 204C modes
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2021-06-10 09:53:43 +03:00 |
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Laszlo Nagy
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680d28476c
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ad9081_fmca_ebz: Add LANE_RATE param to all projects
The block design expects a lane rate to be set in the system project.
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2021-05-14 15:39:40 +03:00 |
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Laszlo Nagy
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da9828a63e
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ad9081:zcu102: Expose parameters to environment
Allow setting project parameters from the environment.
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2021-01-19 17:10:08 +02:00 |
Adrian Costina
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9093a8c428
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
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2020-11-02 16:13:35 +02:00 |
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Laszlo Nagy
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7df4caf8b0
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ad9081_fmca_ebz: Added parameter description
Add parameter description to project and common block design file
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2020-04-23 17:21:05 +03:00 |
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Laszlo Nagy
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f3a7fd8b0d
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ad9081_fmca_ebz:zcu102: initial version
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2020-03-10 18:19:03 +02:00 |