Commit Graph

4152 Commits (b118c6874ef5c2b7e6c3129624d3d2cfcdb9fc5a)

Author SHA1 Message Date
AndreiGrozav cf3737122b Remove duplicare wire declaration
-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
AndreiGrozav 41e25e7c96 Add missing ad_serdes_out interface ports 2017-05-16 19:35:24 +03:00
Rejeesh Kutty c4b4bdc415 daq2/a10gx- constraints remove 16.0 2017-05-16 10:09:42 -04:00
Adrian Costina 0c5dabe358 axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed 2017-05-15 18:59:09 +03:00
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty 63b701ccab altera- add version check 2017-05-12 15:13:29 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty d93a6d062e fmcadc5-sync: added a convenience timer 2017-05-11 12:39:39 -04:00
Istvan Csomortani 8e7b577c94 axi_ad5766: Add missing ports to up_dac_common instance 2017-05-11 17:25:31 +03:00
Istvan Csomortani 6e5d965211 axi_ad5766: sdo_mem size is 3 2017-05-11 17:25:31 +03:00
Istvan Csomortani 7968ca64a6 axi_ad5766: Delete redundant parameters 2017-05-11 17:25:31 +03:00
Istvan Csomortani e327166cf2 axi_generic_adc: Update port names for up_adc_common instance 2017-05-11 11:00:24 +03:00
Rejeesh Kutty 039ae9ae92 fmcadc5- syntax/port name fixes 2017-05-10 16:30:15 -04:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Rejeesh Kutty 6a0a2e4661 hdlmake.pl updates 2017-05-10 14:35:06 -04:00
Rejeesh Kutty 74c44cf830 axi_fmcadc5- remove pack-driver is too late 2017-05-10 14:33:56 -04:00
Rejeesh Kutty c2dd991736 axi_fmcadc5- sign-extend and interleave (core is too late) 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 78435ebbb7 ad9625- add an option to control cs monitoring 2017-05-10 14:33:56 -04:00
Rejeesh Kutty d374f5b091 library/up_adc_common- add sref sync option 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 61bbfb2c82 library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late) 2017-05-10 14:33:56 -04:00
AndreiGrozav c44de7021a axi_ad9739a: Fix DDS set frequency
- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:39:00 +03:00
Istvan Csomortani 5fe008d887 axi_ad9371: Update dac_clk_ratio to 2
DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:12:45 +03:00
Rejeesh Kutty 0e5a24ee7c axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:30:51 -04:00
Rejeesh Kutty b6e9c92f46 axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:29:06 -04:00
Rejeesh Kutty 391a14be7a hdlmake.pl updates 2017-05-04 13:59:47 -04:00
Rejeesh Kutty 1bd444b47f axi_fmcadc5_sync- calcor added 2017-05-04 13:58:35 -04:00
AndreiGrozav f93a003ed1 axi_ad9434: Fix input data rate 2017-05-04 16:43:09 +03:00
Istvan Csomortani 6387b53266 ad77681evb: Initial commit 2017-05-04 12:19:11 +03:00
Istvan Csomortani 3ba57582bb spi_engine_offload: Add a CDC module for trigger reception
There are devices which have a asynchronous data ready signal. (asynchronous
with the spi clock) The CDC stages can be enabled by setting up
the ASYNC_TRIG parameter.
2017-05-04 12:14:06 +03:00
Istvan Csomortani 07956cfe66 spi_engine: Define parameter inside the module statement
Part of the effort to update all verilog files to use the
ANSI-C style port list in module definitions. (verilog-2001)
2017-05-04 12:13:47 +03:00
Istvan Csomortani ef97c1e375 adrv9371x/a10soc: Fix constraints
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
AndreiGrozav f0bc3e20ef zcu102: Automatic IP version update fix 2017-05-02 12:52:43 +03:00
AndreiGrozav cd8f4f23be zcu102: Automatic IP version update 2017-05-02 12:30:00 +03:00
AndreiGrozav d6b09602ed usrpe31x: Automatic IP version update 2017-05-02 12:27:57 +03:00
AndreiGrozav 485c810c2c pzsdr*: Automatic IP version update 2017-05-02 11:43:32 +03:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
Istvan Csomortani f6eea23f5e adaq7980: Update tcl command for IP configuration 2017-04-28 10:12:33 +03:00
Istvan Csomortani 353d1d44da ad5766_sdz: Update tcl commands for IP configuration 2017-04-28 10:12:05 +03:00
Rejeesh Kutty 956753ca9c hdlmake- updates 2017-04-27 15:11:01 -04:00
Rejeesh Kutty 68fc5c89a7 fmcadc5- remove stand alone psync 2017-04-27 15:09:56 -04:00
Rejeesh Kutty 75c7525c60 fmcadc5- remove psync module 2017-04-27 13:29:06 -04:00
Rejeesh Kutty 2027c8427c adi_boadr- disconnect and remove unused ports 2017-04-27 13:26:17 -04:00
Rejeesh Kutty 902eaaaf4c fmcadc5- sync updates 2017-04-27 13:26:17 -04:00