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Author SHA1 Message Date
Iulia Moldovan 68461110aa Replace link in license header from master to main 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2024-01-16 16:48:45 +02:00
PopPaul2021 cd33c99b94 library/axi_ad3552r: Added interface IP for Xilinx projects. 
The custom interface IP for AD3552R DAC has more operation capabilities:
  - 8b register read/write SDR/DDR
  - 16b register read/write SDR/DDR
  - data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
  - selectable input source : DMA/ADC/TEST_RAMP
  - data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
  - the IP reference clock (clk_in) can have a maximum frequency of 132MHz
  - the IP has multiple device synchronization capability when the DMA is set as an input data source

Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
 2023-10-02 11:07:08 +03:00