f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
bf62665c56
prcfg_qpsk: Add Simulink model
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Matlab version used: R2014a, HDL Coder 3.3
2014-11-12 15:44:38 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
cb15567a56
ad6676: added
2014-11-10 13:36:07 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
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This reverts commit b254380338
2014-11-06 12:16:52 +02:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
d69ccebbde
ad9234: full 16bit samples
2014-11-05 11:59:08 -05:00
403fe1b373
wfifo: read only if ready is asserted
2014-10-31 13:05:17 -04:00
38652b1c3e
axi_ad9643: Added constraint file
2014-10-31 17:57:47 +02:00
3e9ce71d21
axi_ad9122: Added constraint file
2014-10-31 17:56:56 +02:00
d596d71285
prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
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This fix the wrong symbol mapping issue.
2014-10-31 12:14:52 +02:00
eb520b1f75
prcfg_qpsk: Major update
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Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
2014-10-31 12:10:59 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
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Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
9818bcb601
axi_fifo2f: internal memory low overhead
2014-10-30 11:12:10 -04:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
6470ea91ad
axi_fifo2f: fake version
2014-10-30 11:12:08 -04:00
f9628262aa
axi_dmac: Add xfer_req signal to the streamin AXI source interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
fbce64411e
axi_ad9671: added synchronization interface to altera core
2014-10-29 18:20:26 +02:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9c8fe5f09c
ad7175: Removed unused files
2014-10-28 14:30:41 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
121a416916
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 13:07:55 +03:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
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Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
46d1710539
axi_ad9625: added constraints
2014-10-17 13:57:30 -04:00
37b608f397
axi_ad9144: added constraints
2014-10-17 13:57:09 -04:00
df3915e2b0
ad9625: constraints added
2014-10-17 13:41:56 -04:00
819a3d0802
util_adc_pack: removed latches
2014-10-17 15:40:16 +03:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
206b96d55a
ip: constraint changes
2014-10-15 14:50:58 -04:00
f0b25c39a3
wfifo: added axi stream support
2014-10-15 14:50:56 -04:00
51a15a28b7
axi_fifo2s: added constraints
2014-10-15 14:50:53 -04:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
3d5ef9a8ed
util_dac_unpack: Fix unpack order with 1 channel
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Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:14 +03:00
dd70320b00
axi_spdif: Add missing signals to the regmap read sensitifity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:09 +03:00
e7af6219dd
axi_spdif: Don't use non-static expressions in port assignments
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Fixes a warning from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:05 +03:00
ab5eee42e4
axi_spdif: Set unused signals to 0
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Fixes warnings about undriven signals from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:00 +03:00
0b587e6fb1
axi_i2s: Add missing signals to the regmap read process sensitivity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:56 +03:00
cf2bbf66b7
axi_i2s: Set unused signals to 0
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Fixes warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:51 +03:00
22169c4a9c
axi_dmac: Add default driver values for optional input ports
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This silences warnings from the tools about undriven ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
e7dbdff60c
axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
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The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00
8557073b56
axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:33 +03:00
3e6f553ce3
axi_dmac: Add clock signal spec for m_axis/s_axis bus
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This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:24 +03:00
c2ed80e8bb
axi_dmac: Drive unused signals to 0
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This silences a few warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:49 +03:00
aee95ebe96
axi_dmac: Fix dummy AXI a{r,w}len fields width
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The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:43 +03:00
4f53a69f3c
util_dac_unpack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:37 +03:00
77133fe60a
util_adc_pack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:29 +03:00
3ab0f417b4
util_dac_unpack: Don't use localparam symbols in input/output signals
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When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:19 +03:00
04e4458ee1
util_dac_unpack: Drive unused ports to 0
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Silences a few warnings about undriven ports from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:12 +03:00
61be003017
axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
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This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:41 +03:00
58cbe1813d
scripts/adi_ip: Add helper function to create bus clock and reset interface
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Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:31 +03:00
a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
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It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
5565cf8fad
axi_ad9467: Independent read/write update
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Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
a436153a48
axi_ad9434: Independent read/write update
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Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
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No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
6a09a1ed19
ad9434: Fix the processor read interface
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Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
2014-09-25 16:51:58 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
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All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
d5f4991e26
ad9434: Merge the ad9434_if interface data outputs into one single bus
2014-09-25 16:45:12 +03:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
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Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
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A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
e528ee0b52
axi_ad9234: axi_ad9680 copy
2014-09-22 11:27:15 -04:00
de0edc2083
axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active
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Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-16 21:02:05 +02:00
c927e90ee1
axi_dmac/axi_fifo: Add missing file
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
17a993032b
util_dac_unpack: Make number of channels and channel width configurable
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Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.
So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:04 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
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By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
36422f0454
axi_dmac: Remove Altera toplevel wrapper
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We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:28:14 +02:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
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Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
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Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
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Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
0da7b6eaa1
axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24
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This is the same as the default value in axi_dmac.v
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:07:35 +02:00
a4b9b1254a
axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
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We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
0966366514
motor_control: Updated the FOC IP
2014-09-08 15:52:18 +03:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
acde4f2c9a
axi_dmac: Added fix to work with motor_control
2014-09-03 12:10:34 +03:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
a773cc4992
usdrx1: updated project
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ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
cf660c126d
util_adc_pack: Fixed problems when working in 4 channels mode
2014-08-29 13:51:40 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
272874f6ad
ad9652: pnmon fixes
2014-08-27 10:44:38 -04:00
31002c404c
util_adc_pack: Added parameters for configuring data width and number of channels
...
Valid values for the number of channels is 4 or 8
Valid values for datawidth is 16 or 32
2014-08-27 14:47:57 +03:00
58fa0776c9
axi_dmac: Added patch to fix issue on altera systems
2014-08-26 16:24:34 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
9438e2a9e0
spdif: constraints file added
2014-08-14 15:09:48 -04:00
1396a215e5
library: local constraints
2014-08-14 15:09:47 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
a5e3a07375
dma: altera fix id assignments
2014-08-11 16:46:36 -04:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
dfd11cb809
ad9467: register map changes
2014-07-30 15:31:09 -04:00
c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
...
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
...
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
...
Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
...
Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
...
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
f3b20fd148
axi_ad9625: register map updates
2014-07-03 11:19:31 -04:00
1a78ac453e
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-07-02 15:39:42 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e4ce00f7fb
axi_ad9680: register map changes
2014-07-02 12:50:09 -04:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen
acozma