8651b7d1e9
fmcjesdadc1/a5soc- 15.1 updates
2016-12-02 13:41:14 -05:00
1e7ab4d708
kcu105- axi-interconnect register slices
2016-12-02 11:54:04 -05:00
108870a2dc
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-08 17:53:32 +03:00
66c02a10de
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-07-28 15:43:35 +03:00
c2ee311ad4
util_dacfifo: Add a bypass option to the FIFO
2016-07-28 15:43:35 +03:00
b611240d46
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-07-22 17:50:18 +03:00
fe08222bdf
Enable bitstream compression for Xilinx projects
...
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 11:40:04 +03:00
136a86adae
a10gx/base: set gpio to 32
2016-05-18 15:26:12 +03:00
93b338eea4
a10gx/base: separate gpio in/out
2016-05-18 15:26:03 +03:00
a51dd941a9
a10gx: Updated base design to include MMU
2016-05-18 11:44:43 +03:00
00d9d4484e
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-05-17 17:16:25 +03:00
c7d3560cb7
arradio: Connect I2C peripheral to the arradio board. Used HPS I2C
2016-05-11 14:20:21 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
...
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
0f37dd6424
fmcjesdadc1: Fixed project
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- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
43e03ca6f7
arradio: Updated project
...
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
a0e67aad56
c5soc: Updated common design
2015-11-24 13:22:01 +02:00
597e9eae84
pzsdr: added ad9361 clock out
2015-11-16 15:53:29 -05:00
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
14bccb6062
pzsdr/ccfmc- rf card/tdd only on fmc
2015-09-22 15:54:53 -04:00
25f3f05c22
pzsdr- breakout + fmc updates
2015-09-18 15:33:50 -04:00
caec400378
pzsdr- make module default
2015-09-18 13:22:01 -04:00
236854c26f
pzsdr-cc-fmc updates
2015-09-18 12:46:42 -04:00
3ef94d559c
rfsom renamed to pzsdr
2015-09-18 11:18:59 -04:00
52d3f189a0
rfsom renamed to pzsdr
2015-09-18 11:18:01 -04:00
0021c7869d
kc705: Deactivated narrow burst support, as it's not needed
2015-09-16 19:02:17 +03:00
d81d8238a9
kc705: Updated mig project file
2015-09-08 16:42:23 +03:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
a67ae238f8
rfsom-ps7- ddr settings
2015-08-31 15:39:45 -04:00
212235189f
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
0e20277bc1
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
93fe70790d
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
810fced1ec
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
6e90ba24e4
rfsom- add rgmii iodelay constraints
2015-08-27 16:26:17 -04:00
3953ab5e22
rfsom- rgmii upgrade
2015-08-27 11:41:55 -04:00
74a6e33f2d
kcu105: 2015.2.1 updates
2015-08-25 09:12:36 -04:00
4eb28592c8
kcu105: 2015.2.1 updates
2015-08-25 09:12:32 -04:00
77e2eb7364
projects/common: Fix parameter name for xilinx core axi_gpio
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Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
d3e090da3d
projects/common: Upgrade Xilinx's IP cores
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To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
AndreiGrozav