38743bf14f
up_axi- writes dropped by delayed w-responses
2016-09-14 17:35:01 +03:00
aa3a821456
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-07-19 09:50:43 -07:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
...
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
...
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
9ba8c059ce
ad_tdd_sync: Fix reset value of the pulse_counter
2015-11-13 18:31:24 +02:00
3c27b3a4c5
ad_lvds_in: Add single ended option
2015-11-13 12:13:09 +02:00
b17fec689e
ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
...
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
...
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
96d363849e
ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block
2015-10-09 13:43:14 +03:00
5c3f90a676
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
97a9ecfc9a
axi_hdmi_rx: Update constraint file and fix reset line
2015-09-29 18:49:30 +03:00
b765be568f
up_gt_channel: Delete the register, which stores transceiver type
...
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
cffb2e6226
up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
2015-09-29 14:19:52 +03:00
a0ac0e912b
up/ad_gt_common/channel: Cosmetic changes
2015-09-29 14:16:24 +03:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
...
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
884f45c81d
common library: Registered dc_filter and iq_correction coefficients
2015-09-16 14:24:18 +03:00
5bc16159fa
ad_tdd_sync: The resync will reset all the control lines
2015-09-10 11:28:36 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
...
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
Rejeesh Kutty
Matthew Fornero
AndreiGrozav
Adrian Costina
Istvan Csomortani