b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
20d59ce39b
daq2: dma fifo modifications
2014-10-22 16:39:28 -04:00
4eeb50114f
daq2: rebase conflicts
2014-10-22 16:39:17 -04:00
43cdafe1e2
kcu105: iic-rstn removed
2014-10-22 16:33:52 -04:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
43fe20d141
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-22 17:19:37 +02:00
dcdba475f7
vc707_common: Fix net name sys_100m_resetn
2014-10-22 15:41:36 +03:00
a0d27a117c
usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints
2014-10-22 13:20:44 +03:00
cd9033296c
ad9671_fmc: Fixed constraint files
2014-10-22 13:14:59 +03:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
121a416916
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 13:07:55 +03:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
767179dce9
adv7511_zc706: Fix IRQ layout
...
Fix IRQ connection, this layout works on Linux
2014-10-21 17:44:28 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
...
Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
2beaeb9176
projects/daq2/kcu105/system_constr.xdc: temp constrains
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
8a4ab4e05a
projects/ad9434_fmc/common/ad9434_bd.tcl: Fix freeze - Design doesn't use SYNC
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
d4a21d9775
ad9625_fmc: constraints fix
2014-10-20 10:00:39 -04:00
b3c784f76a
ad9467_fmc: Made some cosmetic changes on the block design script.
2014-10-20 13:28:34 +03:00
4b8720b551
fmcomms2_zc706: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:25:01 +03:00
7115864b4c
ad9434_fmc: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:23:37 +03:00
5deffd57b1
zed: Remove top level constraints
...
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
0c56e5b912
ad9434_fmc: Fix GPIO width
...
GPIO port width is 15 instead of 32
2014-10-20 10:59:30 +03:00
7f8270d74b
ad9625_fmc: generic dma fifo for zynq and non-zynq boards
2014-10-17 14:38:16 -04:00
0b30f98640
ad9625_fmc/zc706: remove top level constraints
2014-10-17 14:38:15 -04:00
f3c9627cae
adi_project: demote reset warnings to info
2014-10-17 14:38:13 -04:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
46d1710539
axi_ad9625: added constraints
2014-10-17 13:57:30 -04:00
37b608f397
axi_ad9144: added constraints
2014-10-17 13:57:09 -04:00
380eeec013
daq2/kcu105: ethernet fix
2014-10-17 13:48:35 -04:00
fca0714478
adv7511/kcu105: ethernet fix
2014-10-17 13:48:33 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
df3915e2b0
ad9625: constraints added
2014-10-17 13:41:56 -04:00
cccef98e2b
util_adc_pack: removed latches
2014-10-17 15:44:21 +03:00
819a3d0802
util_adc_pack: removed latches
2014-10-17 15:40:16 +03:00
2600b1f359
daq3: tx interleave and dma fifo axi streaming
2014-10-15 14:51:04 -04:00
6d76e0b768
zc706: remove top level constraints
2014-10-15 14:51:02 -04:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
206b96d55a
ip: constraint changes
2014-10-15 14:50:58 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
f0b25c39a3
wfifo: added axi stream support
2014-10-15 14:50:56 -04:00
0aed11fa6c
adi_project: demote useless warnings
2014-10-15 14:50:54 -04:00
51a15a28b7
axi_fifo2s: added constraints
2014-10-15 14:50:53 -04:00
4d4a7981f2
fmcomms1: Connect DMA controller directly to the HP ports
...
The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:46:07 +03:00
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
d2a04856a9
common: Fix xlconstant output pin name
...
On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
02802644bf
fmcjesdadc1: Fix a few warning and issue with ILA
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+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
acozma
Rejeesh Kutty
Michael Hennerich
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen