Commit Graph

8 Commits (acbbd4636a459030d3d9ace1e20b485abfa13d65)

Author SHA1 Message Date
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Laszlo Nagy b90c2e79dc jesd204_rx: add parameter for input pipeline stages
Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
Adrian Costina 3b9f733408
jesd204: Add RX error statistics (#98)
* jesd204: Add RX error statistics

Added 32 bit error counter per lane, register 0x308 + lane*0x20

On the control part added register 0x244 for performing counter reset and counter mask
Bit 0 resets the counter when set to 1
Bit 8 masks the disparity errors, when set to 1
Bit 9 masks the not in table errors when set to 1
Bit 10 masks the unexpected k errors, when set to 1

Unexpected K errors are counted when a character other than k28 is detected. The counter doesn't add errors when in CGS phase

Incremented version number
2018-05-07 15:33:00 +03:00
Istvan Csomortani 0e099b6f08 jesd204_rx: Add dynamic multi-link support
A multi-link is a link where multiple converter devices are connected to a
single logic device (FPGA). All links involved in a multi-link are synchronous
and established at the same time. For a RX link this means that the SYNC signal
needs to be propagated from the FPGA to each converter.

Dynamic multi-link support must allow to select to which converter devices on
the multi-link the SYNC signal is propagated too. This is useful when depending
on the usecase profile some converter devices are supposed to be disabled.

Add the cfg_links_disable[0x081] register for multi-link control and
propagate its value to the RX FSM.
2018-05-03 18:48:54 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen dd1b1c89f9 jesd204: jesd204_rx: Don't expose internal states on the status interface
The DEGLITCH state of the RX state machine is a workaround for misbehaving
PHYs. It is an internal state and an implementation detail and it does not
really make sense to report through the status interface.

Rework things so that DEGLITCH state is reported as part of the CGS state
on the external status interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen 2d896c0729 jesd204: Add Altera/Intel IP support
Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204
peripherals. This allows them to be instantiated and used on Altera/Intel
platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:09:42 +02:00