Adrian Costina
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2dfcb0c599
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usdrx1: Initial commit for a5gt
axi_ad9671: added start of frame information to the altera core.
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2014-10-07 19:41:54 +03:00 |
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acostina
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296983707b
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usdrx1: Updated project to 2014.2
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2014-09-23 22:45:50 -04:00 |
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acostina
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5af2474d51
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usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
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2014-09-23 22:44:33 -04:00 |
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Adrian Costina
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bdf01738a1
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ultrasound: disconnected ADN4670 chips from SPI lines.
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
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2014-09-23 22:30:42 -04:00 |
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Adrian Costina
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d33fb07587
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usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
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2014-09-16 15:56:19 -04:00 |
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Adrian Costina
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d4db53c3b0
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usdrx1_spi: Modified module to be compatible with altera
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2014-09-16 15:53:11 -04:00 |
Lars-Peter Clausen
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50faf0c53a
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Remove executable flags from non-exectuable files
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2014-09-09 15:05:06 +02:00 |
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Adrian Costina
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a773cc4992
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usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
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2014-09-01 15:18:39 +03:00 |
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Adrian Costina
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6e444559b5
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usdrx1: global clock fix
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2014-06-10 18:09:49 +03:00 |
Rejeesh Kutty
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38126c404c
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usdrx1: spi signal definitions
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2014-04-11 14:28:23 -04:00 |
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Rejeesh Kutty
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06b28d2e24
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ad9671: compile fixes
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2014-04-11 14:28:22 -04:00 |
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Rejeesh Kutty
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96541f0a7f
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usdrx1: zc706 updated for usdrx1
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2014-04-10 11:05:13 -04:00 |
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Rejeesh Kutty
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6f36f74eea
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usdrx1: common board files
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2014-04-10 11:05:11 -04:00 |
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Rejeesh Kutty
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ac1c145a61
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usdrx1: initial checkin
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2014-04-10 11:05:10 -04:00 |