Adrian Costina
|
9cdd4107cd
|
fmcomms5: ZC702: add reset_b and fixed system_top
|
2014-07-25 15:24:11 +03:00 |
|
Adrian Costina
|
26a019ae6e
|
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
|
2014-07-25 10:20:49 +03:00 |
Rejeesh Kutty
|
7bee85423d
|
c5soc: removed stp/cdf files
|
2014-07-24 20:53:08 -04:00 |
|
Rejeesh Kutty
|
59759a8ab3
|
c5soc: working hdl version
|
2014-07-24 20:51:41 -04:00 |
|
Rejeesh Kutty
|
6346017763
|
c5soc: changed to alt_lvds - 250M is too high for cyclone v
|
2014-07-24 20:51:40 -04:00 |
|
Adrian Costina
|
7000897031
|
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
|
2014-07-24 19:57:22 +03:00 |
|
Adrian Costina
|
a68f634de9
|
fmcomms5: Added resetb for the second AD9361
|
2014-07-24 17:31:30 +03:00 |
|
Rejeesh Kutty
|
701dc96016
|
up_dac_channel: make iq cor coeff(s) tc
|
2014-07-24 10:10:24 -04:00 |
Istvan Csomortani
|
49a77c0413
|
prcfg: Generate configuration files to *.bin
|
2014-07-24 09:43:00 +03:00 |
|
Istvan Csomortani
|
191f994e79
|
prcfg: Fixed the PRBS lock issue on BIST
|
2014-07-24 09:41:13 +03:00 |
|
Rejeesh Kutty
|
db2386a351
|
daq2/kcu105: latest mig updates
|
2014-07-23 16:25:55 -04:00 |
|
Istvan Csomortani
|
db1c931736
|
ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
|
2014-07-23 19:34:44 +03:00 |
|
Istvan Csomortani
|
4da8100fe5
|
ad9625_plddr: Delete trailing whitespaces.
|
2014-07-23 19:31:07 +03:00 |
|
Adrian Costina
|
54b2cd74bf
|
motor_control: cores modified so they can compile with the new common files
|
2014-07-23 11:58:50 +03:00 |
|
Rejeesh Kutty
|
c0e31aa6c2
|
daq2: latest hardware
|
2014-07-21 09:06:57 -04:00 |
|
Rejeesh Kutty
|
e3320c43cb
|
fmcomms2/c5soc: programmer file
|
2014-07-21 09:06:55 -04:00 |
|
Rejeesh Kutty
|
9b9e0c6a56
|
fmcomms2/c5soc: signal tap
|
2014-07-21 09:06:54 -04:00 |
|
Rejeesh Kutty
|
65879d621f
|
daq2: updates for the new hardware
|
2014-07-21 09:06:53 -04:00 |
|
Istvan Csomortani
|
2b6ce1e504
|
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
|
2014-07-21 15:10:36 +03:00 |
|
Rejeesh Kutty
|
2955b9db78
|
fifo2s: flush if no request, c5soc: 14.0
|
2014-07-15 16:25:33 -04:00 |
|
Rejeesh Kutty
|
e7d5d79e42
|
daq2/kcu105: gth up and running - as it is commit
|
2014-07-10 10:56:37 -04:00 |
|
Istvan Csomortani
|
085512a738
|
fmcomms2_pr: Fix the source path for prcfg_setup
|
2014-07-10 17:54:41 +03:00 |
|
Istvan Csomortani
|
95701fbd0e
|
fmcomms2_pr : PR initial check in
|
2014-07-10 10:41:48 +03:00 |
|
Rejeesh Kutty
|
a9992f02b0
|
fifo2s: bug fixes- on 64mhz dma clock
|
2014-07-08 16:57:44 -04:00 |
|
Rejeesh Kutty
|
b434fe6dd5
|
fmcomms5: register map changes
|
2014-07-08 16:57:43 -04:00 |
|
Istvan Csomortani
|
dc78ced443
|
prcfg_lib: Change the prcfg_top interface
Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
|
2014-07-08 12:28:25 +03:00 |
|
Istvan Csomortani
|
75e624ef15
|
prcfg_lib: Flop the status and mode nets
Flop the status and mode nets in case of BIST and QPSK configurations.
|
2014-07-08 12:23:48 +03:00 |
|
Adrian Costina
|
39ac29bb01
|
AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
|
2014-07-08 10:41:51 +03:00 |
dbogdan
|
10c21a343a
|
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
|
2014-07-08 10:07:31 +03:00 |
|
dbogdan
|
c53b257ab1
|
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
|
2014-07-07 22:28:25 +03:00 |
|
Rejeesh Kutty
|
c75e6b3043
|
kcu105 pwr-good removed
|
2014-07-07 09:56:13 -04:00 |
|
Rejeesh Kutty
|
f2bf5ced04
|
ad9625: register map updates
|
2014-07-03 14:30:03 -04:00 |
|
Rejeesh Kutty
|
f94cbbb0aa
|
daq2: register map updates
|
2014-07-03 12:36:37 -04:00 |
|
Rejeesh Kutty
|
f3b20fd148
|
axi_ad9625: register map updates
|
2014-07-03 11:19:31 -04:00 |
|
Rejeesh Kutty
|
1a78ac453e
|
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
|
2014-07-02 15:39:42 -04:00 |
|
Rejeesh Kutty
|
a388ccab0a
|
fmcomms2/c5soc: initial checkin
|
2014-07-02 14:56:00 -04:00 |
|
Rejeesh Kutty
|
e4ce00f7fb
|
axi_ad9680: register map changes
|
2014-07-02 12:50:09 -04:00 |
|
Istvan Csomortani
|
7e5748374d
|
prcfg_lib: Fixed prbs generator for QPSK
|
2014-07-02 18:14:35 +03:00 |
|
Istvan Csomortani
|
8eb7a55797
|
prcfg_lib: Fixed the gpio status merge logic
The previous logic did not passed implementation.
|
2014-07-02 18:09:48 +03:00 |
|
Istvan Csomortani
|
9089877c70
|
prcfg_lib: Fixed the sine tone generator for BIST
|
2014-07-02 18:00:43 +03:00 |
Lars-Peter Clausen
|
8a2b29cdbe
|
axi_damc: Add xfer_req to the FIFO source interface
The xfer_req signal will be high if DMA core the is expecting data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
|
2014-07-02 16:05:16 +02:00 |
|
Rejeesh Kutty
|
31abd07613
|
axi_ad9144: register map changes
|
2014-07-01 21:43:04 -04:00 |
|
Rejeesh Kutty
|
9a08189b93
|
c5soc: initial a5soc copy
|
2014-07-01 13:09:38 -04:00 |
|
Rejeesh Kutty
|
c1b7fc17f5
|
c5soc: initial a5soc copy
|
2014-07-01 13:05:26 -04:00 |
|
Rejeesh Kutty
|
60dd14bcdb
|
a5soc: removed jtag master control
|
2014-07-01 12:27:37 -04:00 |
|
Rejeesh Kutty
|
b6052773b7
|
added adc/dac gpio registers
|
2014-06-27 14:45:58 -04:00 |
|
Rejeesh Kutty
|
ba7955c531
|
fmcomms2: register map modifications
|
2014-06-26 10:09:03 -04:00 |
|
Rejeesh Kutty
|
4afe6c24e9
|
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
|
2014-06-25 15:26:21 -04:00 |
|
Rejeesh Kutty
|
10a7804e14
|
ad9361: altera wrapper updates
|
2014-06-25 15:26:06 -04:00 |
|
Rejeesh Kutty
|
92e525d573
|
ad9250: register map updates
|
2014-06-25 15:24:48 -04:00 |