2 Commits (aa070ef9404c51d5552fbf30442279ea913de6d3)

Author	SHA1	Message	Date
Laszlo Nagy	0261eade0c	zynq:all: fix SPI clock constraint ... According to data sheets the EMIO SPI controller maximum frequency is just 25MHz. Constrain the SPI clock accordingly.	2019-08-09 16:39:56 +03:00
Rejeesh Kutty	2ececad58c	sdrstk-2-pluto	2016-11-11 13:49:04 -05:00