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5 Commits (a8a71b49714872398f9973ee0fc9d42c5520549e)

Author SHA1 Message Date
Istvan Csomortani 0e1a60e8b7 axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface. 2015-03-26 12:20:32 +02:00
Lars-Peter Clausen aa594e15f3 axi_dmac: fifo_inf: Handle overflow and underflow correctly 
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-02-19 17:22:21 +01:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 20:59:13 +01:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00