aa7b0bb4dd
VC707 basesys: General fixes, actual status: working
...
- Add an auxiliary cpu interconnect
- Add an auxiliary interrupt concatenation module
- Add new MIG file, current frequency of the DDR interface is 100
Mhz
- Memory interconnect optimisation strategy is 'Maximize
Performance'
2014-03-24 13:07:48 +02:00
b94acf78aa
AC701 bases sys: Add an auxiliary cpu interconnect
...
- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
2014-03-24 13:01:52 +02:00
792e8a208d
KC705 base system: Make a few cosmetic changes
2014-03-24 12:55:37 +02:00
8a08031dce
AC701: Modify interrupt concatenation
...
- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
a6da4ca01c
zynq/non-zynq merge variables
2014-03-17 16:39:52 -04:00
75963ab376
Initial check in of VC707 base project
...
- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
b0a1fab743
adv7511/kc705: added
2014-03-05 10:43:16 -05:00
82115b138e
adv7511/ac701: initial checkin
2014-03-03 13:40:24 -05:00
c89477be5a
projects/adv7511: zynq boards
2014-03-03 10:16:49 -05:00
Istvan Csomortani
Rejeesh Kutty