Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
Lars-Peter Clausen
István Csomortáni
Rejeesh Kutty
Istvan Csomortani
Adrian Costina