On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
In some cases, the Vivado version can contain other characters than just
numbers. One such example is after applying the patch of AR# 71948,
which makes `version -short` return something like `2018.3_AR71948`.
This patch changes the version check to ignore anything after the first
two components of the version.
Add definition for new ultrascale device packages.
The package information is used by software for xcvr calibration.
At the moment, the factors that are influencing the calibration for the new
packages are not clear.
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
Use over-writable parameters from the environment.
e.g.
make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.
By using the streaming mechanism the interface is simplified and the
above problems are solved.
For Intel projects:
In cases where the clock of source synchronous interface is not routed
through a clock capable pin the DPA receive mode can't be used. Instead
the clock will be routed through a clock buffer from an IO to the clock
tree and from there to the IOPLL.
Because fmcomms2 was not supported on a Intel carriers the
fmcomms2_qsys.tcl file got outdated.
The arradio project has the same hdl design. Hence the update is
merely a copy of the arradio_qsys.tcl with small changes.
This commit fixes the critical warning regarding the missing clock
definitions.
- Defined MDC(MDIO) clocks
- Set false path on(to) the ps8 MDIO input pins. There are synchronization
stages in the GMII to RGMII converter for the CDC between the 375M refclk
and 2.5M MDC clock domains.
Laszlo Nagy
Mathias Tausen
Maxim
AndreiGrozav
Istvan Csomortani
Adrian Costina
sarpadi
StancaPop