Commit Graph

8 Commits (a3cd70ff1dc62ea13ef0f25034e2218fda3829b7)

Author SHA1 Message Date
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty a74c61d6d5 vc707: gpio_bd changes 2015-03-23 10:00:46 -04:00
Adrian Costina 69326a72ef VC707: Updated base design 2015-03-20 18:20:44 +02:00
Istvan Csomortani e8ff30119d vc707_xdc: Delete unnecessary clock definition 2015-01-29 11:39:10 +02:00
Adrian Costina 05ed98f884 common: Updated common constratins for ac701, kc705, vc707, zc702 2014-11-11 12:35:44 +02:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00