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Author SHA1 Message Date
Alin-Tudor Sferle a031cba1d5 project_xilinx.tcl: Fix the regex expression for Kria KV260 evaluation board 2023-07-19 11:32:10 +03:00
Iulia Moldovan 86c9847c5f Add copyright & license to .sh, .yml, .pl files. Edit Makefile for KV260 
* Updated the Makefile for KV260 template as the copyright was not generated
   properly

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 18:39:55 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
AndreiGrozav 8b15d66302 Rename pluto_ng to jupiter_sdr plus RevB updates 
Update license according to the latest format
 2023-06-30 09:14:07 +03:00
Bogdan Luncan 3f0a487b2e ad9082/vck190: Add initial design 
ADC Mode 27: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS
DAC Mode 35: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-16 12:13:55 +03:00
Bogdan Luncan 80fe536863 ad9081/vck190/system_project: Change the default profile 
ADC Mode 26: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS
DAC Mode 24: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-16 12:13:55 +03:00
Bogdan Luncan 294b681196 ad9081: Proper reset sequence for versal transceivers 
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge

ad9209/vck190/system_top: Connect versal transceiver reset

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-16 12:13:55 +03:00
alin724 e530b3feec adrv9001_zcu102: Reduce allowed clock skew for rx*_dclkout in lvds_constr.xdc 2023-05-15 11:41:56 +03:00
Iulia Moldovan d18ea43bb6 m2k: Fix CW for slave segments without an address space 
The following CWs appeared (even in Vivado version 2021.2):
 * CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_logic/m_axi>. Please use Address Editor to either assign or exclude it.
 * CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_converter/m_axi>. Please use Address Editor to either assign or exclude it.

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-05-15 10:40:27 +03:00
alin724 0f3462c83b template_kv260: Add template design for kv260 evaluation board 2023-05-12 16:06:19 +03:00
LIacob106 830b5aecb6 projects: 9009: system_project.tcl: List configs as comments 
Add a list with make commands with the proper parameters for each devicetree
availible at the moment.

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-05-12 14:17:05 +03:00
Bogdan Luncan b03fac4b37 ad9209: Initial vck190 design 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Bogdan Luncan e1af7837da ad9081: Parameters and header update 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Bogdan Luncan b21fb3a0e0 ad9081/common: Added ad9081_fmc.txt 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Bogdan Luncan 73af87a324 ad9081: Versal transceiver update 
- Remove 4 lane limitation
- Adds support for RX or TX only instantiation

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Filip Gherman 5776511dd7 vcu118: Improve Microblaze Cache Performance for a better timing closure 2023-05-04 10:40:43 +03:00
Filip Gherman 2db55675f9 vcu128_system_bd.tcl: Additional microblaze interrupt for VCU128 2023-05-04 10:40:01 +03:00
Iulia Moldovan ea603b12a7 project-xilinx.mk: Update folders and files from make clean 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-04-28 17:02:13 +03:00
PIoandan 6a016c62db kc705 vc707: Increase linear flash capacity 2023-04-26 10:08:52 +03:00
Stanca Pop 1c8f210baf adi_project_xilinx.tcl: Add matlab env variables 
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.

The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.

The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
 2023-04-21 15:41:42 +03:00
ladace 4dee04f9c8
cn0561:de10nano: Updated Quartus version to 22.1Std (#1116) 2023-04-13 13:19:51 +03:00
ladace 34984e67c2
Quartus: Updated to Quartus Standard 22.1 (#1108) 2023-04-05 09:36:46 +03:00
sergiu arpadi cadb8e637d cn0561_de10nano: Initial commit 2023-03-30 14:55:59 +03:00
Sergiu Arpadi 4b704337d4 cn0540_de10nano: Update system_top, cleanup 2023-03-30 14:55:59 +03:00
alin724 7da9827782 ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter 2023-03-29 21:33:33 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies 
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 1bef2bf304 projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 
* Updated bd spi hierarchy, see library/spi_engine.tcl
 * Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 553774319a projects/cn0561: Update design: spi trigger, ODR, spi hierch 
* Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Stanca Pop ee30c64923 projects/ad4134_fmc: Initial commit add support 
* Updated reference design: spi trigger, ODR parameters
  - enabled ext_clk for PWM to use 96 MHz spi clk
  - mofified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
  - spi offload trigger signal: PWM trigger used
 * Moved mem_interconnect to hp1
 * Added dclkio GPIO
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl 
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
 2023-03-29 15:08:07 +03:00
Paul Pop 890569d53f projects/cn0579/de10nano: Fix Critical Warnings 
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year

Signed-off-by: Paul Pop <paul.pop@analog.com>
 2023-03-24 09:09:15 +02:00
Jem Geronimo 75adcb4e37
adi_project_intel.tcl: bugfix for ad_project_dir (#1101) 
bug:
  say "make LVDS_CMOS_N=0"
  - will set ad_project_dir as LVDSCMOSN0
  - will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
  - build error reveals system_bd can't be found
  - maybe due to setting ad_project_dir as a relative file path
fix:
  - set ad_project_dir as an absolute file path

Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
 2023-03-17 19:09:33 +08:00
Paul Pop b84d50bbb3 projects/cn0579: Initial commit for Coraz7s and DE10Nano 2023-03-16 16:20:44 +02:00
Iulia Moldovan 9977df074b vmk180_system_bd.tcl: Fix issue with PMC_I2C_PERIPHERAL 
* Issue appeared when updating to Vivado 2022.2

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-03-09 09:53:41 +02:00
alin724 341ade7ae0 ad7606x: Fix system_top module's gpio instances and add missing adc_serpar,_refsel pins 2023-03-08 13:06:03 +02:00
PopPaul2021 2f7c8edef0 projects/*/a10gx: Support for A10GX carrier is discontinued. 2023-03-01 14:55:18 +02:00
Istvan-Zsolt Szekely 72461b2218 adi_board.tcl: Support multiple common channels connections between different TX adxcvr's and util_xcvr 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
 2023-02-09 17:08:18 +02:00
AndrDragomir a8a01aaaf4 projects/adrv9009zu11eg: Fix lane swap on tx1_c when used with fmcomms8 2023-02-03 11:00:33 +02:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
LIacob106 e932e6f4f8 projects/adrv9009zu11eg: JESD support for fmcomms8 
for configurations 4, 8 TX_L and 4 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 261c0d1b90 projects/adrv9009zu11eg: JESD support for adrv2crr_fmc 
for configurations 2, 4 TX_L and 2 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 9b8604b9a2 adrv9009/zc706: Add clkgen div to match the desired freq 2023-01-26 15:36:45 +02:00
LIacob106 911b8bbc99 projects/adrv9009: JESD support for 1, 2 TX_L and 1 RX/ORX_L 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:36:45 +02:00
LIacob106 10a87f34d3 projects/fmcomms8: Interconnect m_axi port for rx_xcvr 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:35:12 +02:00
Filip Gherman 4c1f68b119 vcu118_system_bd.tcl: Additional microblaze interrupt for VCU118 2023-01-17 13:31:16 +02:00
alin724 189624a655 ad7606x_fmc: Initial commit 2023-01-12 17:38:14 +02:00
LIacob106 19249b51db projects/fmcomms8: JESD support for 2, 4 TX_L and RX/ORX_L 
On zcu102 carrier.

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-10 13:06:23 +02:00
sergiu arpadi 1b1cbfc8ef ad4110: Initial commit 2022-12-14 15:01:16 +02:00
Ionut Podgoreanu a3e1e6286b ad9081_fmca_ebz_x_band: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00