cadb8e637d
cn0561_de10nano: Initial commit
2023-03-30 14:55:59 +03:00
2ae09c9808
Check guidelines. Remove redundancies
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* Removed empty/commented lines
* Regenerated Makefiles
* Removed redundancies adc channels data width
* Set data width 32-bit: max resolution and CRC header
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
553774319a
projects/cn0561: Update design: spi trigger, ODR, spi hierch
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* Enabled ext_clk for PWM to use 96 MHz spi clk
* Modified PWM channels used:
- ch1: ODR - 850 ns period, 130 ns high time
==> max fODR = 1.18 MHz
- ch0: trigger - 850 ns period, 30 phase shift
==> 10 ns between falling ODR rising DCLK
* Changed spi offload trigger signal:
- replaced edge detect,sync_bits IPs with PWM trigger
* Updated bd SPIE hierarchy, see library/spi_engine.tcl
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects ( #1023 )
2022-09-29 15:14:57 +03:00
8a77d4fb05
coraz7s: Memory interconnect fix ( #1014 )
2022-09-23 14:58:43 +03:00
0ac49027bd
cn0561_coraz7s: Initial commit
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Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
2022-05-11 17:30:26 +03:00
sergiu arpadi
laurent-19
PopPaul2021