Commit Graph

7 Commits (a031cba1d5bbaf6f4574d33d7c6ba455eb15e3eb)

Author SHA1 Message Date
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 8213d8a916 cn0363: Update block design
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
Istvan Csomortani 8eb65186e9 cn0363: Reorder the configuration settings of the fir filters
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00
Istvan Csomortani 0cfef974a6 cn0363: Fix typos and mistakes made in 0737183 2017-04-24 12:43:33 +03:00
Istvan Csomortani 073718315a cn0363: Update IP instantiations 2017-04-21 15:06:06 +03:00
Lars-Peter Clausen 514eb68876 cn0363: Factor out common parts
Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00