Commit Graph

869 Commits (a0039ed4fe409124ff58ff6ff0e2f9164854e77b)

Author SHA1 Message Date
Lars-Peter Clausen acd9efc528 axi_hdmi_tx: Add parameter to configure the output clock polarity
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Rejeesh Kutty 88568c21e1 util_gtlb: updates for latest axi_jesd_gt 2015-10-30 18:47:36 -04:00
Rejeesh Kutty 2b6ae00a44 library: add mfifo 2015-10-27 14:52:02 -04:00
Rejeesh Kutty f1ed27105f library/common- reset fix 2015-10-23 14:32:35 -04:00
Adrian Costina 32b3cfd8b9 axi_usb_fx3: Initial commit of the core with interface stub 2015-10-23 13:27:00 +03:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani 6fb56079ee library/util_gtlb: Add Makefile 2015-10-16 13:58:01 +03:00
Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Rejeesh Kutty 44568f1f64 util_jesd_gt: bad idea, it is needed for ipi 2015-10-15 11:13:08 -04:00
Rejeesh Kutty a6ff1b13fc util_jesd_gt- remove unused parameters 2015-10-15 10:46:07 -04:00
Istvan Csomortani c9a5057b93 library/prcfg : Split data bus to channels
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
Adrian Costina a753d506c5 axi_mc_controller: Removed channels, as no data needs to be streamed to DMA 2015-10-09 13:54:03 +03:00
Adrian Costina 694dbd3259 axi_mc_controller: Updated constraints 2015-10-09 13:53:13 +03:00
Adrian Costina 7c3646e863 axi_mc_current_monitor: Removed stub channel 2015-10-09 13:52:14 +03:00
Adrian Costina 99e6240126 axi_mc_current_monitor: Updated constraints 2015-10-09 13:51:15 +03:00
Adrian Costina d19d9c8fbc axi_mc_speed: Corrected maximum number of channels 2015-10-09 13:50:25 +03:00
Adrian Costina ce01185348 axi_mc_speed: Updated constraints 2015-10-09 13:50:08 +03:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Adrian Costina df8ac2e726 axi_ad9671: Updated constraints 2015-10-09 13:15:55 +03:00
Adrian Costina 03b225a802 axi_ad9671: Fixed synchronization mechanism 2015-10-09 13:15:12 +03:00
Istvan Csomortani 8321d5a4fb util_dacfifo: Update read out method
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
Rejeesh Kutty cd9754afbe up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty f3ffd5a63f up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 2b894bc13e up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 5c3f90a676 up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty ba70c7a4ea ad9144- ip updates 2015-09-30 11:37:10 -04:00
Rejeesh Kutty 54fcf06eed ad9152- ip updates 2015-09-30 11:34:09 -04:00
Istvan Csomortani 81a1c21553 util_pmod_adc: Reset line changed to active low reset. 2015-09-30 12:33:46 +03:00
Istvan Csomortani 97a9ecfc9a axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
Istvan Csomortani b765be568f up_gt_channel: Delete the register, which stores transceiver type
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
Istvan Csomortani cffb2e6226 up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
Istvan Csomortani a0ac0e912b up/ad_gt_common/channel: Cosmetic changes 2015-09-29 14:16:24 +03:00
Adrian Costina dff6c0df01 axi_ad9652: Updated with the latest constraints 2015-09-28 11:29:07 +03:00
Istvan Csomortani c03983ca54 ad_tdd_sync/control: Update TDD logic
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
Istvan Csomortani 07e2d281c0 Make: Update Make files 2015-09-25 19:11:21 +03:00
Istvan Csomortani 884973fdbb util_dacfifo: Cosmetic changes 2015-09-25 17:41:44 +03:00
Adrian Costina 2816812e0a axi_ad9625: Updated constraints and added adc reset port 2015-09-25 17:16:31 +03:00
Adrian Costina 37a4e976d6 axi_ad6676: Updated constraints 2015-09-25 17:02:42 +03:00
Adrian Costina 061f468fb1 axi_ad9250: Update library
- added adc reset port
- addded common constraints
2015-09-24 19:10:19 +03:00
Istvan Csomortani ebaebc54f7 axi_ad9680: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:29 +03:00
Istvan Csomortani 9ad59c58db axi_ad9234: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:18 +03:00
Istvan Csomortani 0b08250261 axi_ad9152: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:08 +03:00
Istvan Csomortani 892755c084 axi_ad9144: Clock ratio is indicating a sampling clock ratio
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:18:48 +03:00
Istvan Csomortani 900db3d8ed util_wfifo: Fix reset related timing violation
The memory instance reset connected to ground, rather than connect to dout_rstn.
2015-09-23 16:36:33 +03:00
Istvan Csomortani 516c59523d util_wfifo: Cosmetic changes. 2015-09-23 16:36:31 +03:00
Istvan Csomortani 568333bbfc axi_dmac: Fix typo on ./bd/bd.tcl 2015-09-23 15:51:50 +03:00
Istvan Csomortani aa608e3907 axi_ad9467: Update constraints 2015-09-23 14:26:57 +03:00
Istvan Csomortani 0411ad2386 axi_ad9434: Update constraints 2015-09-23 14:26:55 +03:00
Lars-Peter Clausen cd93beb10f util_axis_fifo: Remove m_axis_addr_next output from the address modules
Remove m_axis_addr_next output from the address modules since it is no
longer used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 5c22e622de axi_dmac: Fix width for dest response FIFO
The width of the dest response FIFO is 1 bit not 3 bits.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00