2 Commits (9fa3131858fcb9758854b4c4fa9e1cf24e6da7cc)

Author	SHA1	Message	Date
Istvan Csomortani	19732d89fb	plddr3: Fix the adc_dwr pulse width ... The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.	2014-12-09 13:51:00 +02:00
Rejeesh Kutty	81b4cd532d	axi_fifo2s: include bus width/clock transfer	2014-11-12 14:43:38 -05:00