0eaa98370e
fmcadc2/vc707- spi clock reg can't be on iob
2017-05-19 15:22:33 -04:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
86512ad95a
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:10 -04:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Adrian Costina